R8C2K datasheet(219/471 Pages) RENESAS

219 / 471 page

R8C/2K Group, R8C/2L Group

16. Timers

Rev.1.10

Dec 21, 2007

Page 202 of 450

REJ09B0406-0110

Figure 16.52

Operating Example of Output Compare Function

Output level held

TRC register value

Count source

m+1

TSTART bit in

TRCMR register

TRCIOA output

IMFA bit in

TRCSR register

n+1

TRCIOB output

“H” output at

compare match

Set to 0 by a program

IMFB bit in

TRCSR register

Initial output “L”

TRCIOC output

Set to 0 by a program

IMFC bit in

TRCSR register

Initial output “H”

“L” output at compare match

P+1

m: TRCGRA register setting value

n: TRCGRB register setting value

p: TRCGRC register setting value

The above applies under the following conditions:

Count

restarts

Count

stops

Output level held

Set to 0 by a program

• Bits BFC and BFD in the TRCMR register are set to 0 (TRCGRC and TRCGRD do not operate as buffers).

• Bits EA, EB, and EC in the TRCOER register are set to 0 (output from TRCIOA, TRCIOB, and TRCIOC enabled).

• The CCLR bit in the TRCCR1 register is set to 1 (set the TRC register to 0000h by TRCGRA compare match).

• In the TRCCR1 register, bits TOA and TOB are set to 0 (“L” initial output until compare match) and the TOC bit is set to 1 (“H” initial output until

compare match).

• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 011b (TRCIOA output inverted at TRCGRA compare match).

• Bits IOB2 to IOB0 in the TRCIOR0 register are set to 010b (“H” TRCIOB output at TRCGRB compare match).

• Bits IOC2 to IOC2 in the TRCIOR1 register are set to 001b (“L” TRCIOC output at TRCGRC compare match).

Output level held

Output inverted at

compare match

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