R8C2K datasheet(160/471 Pages) RENESAS

160 / 471 page

R8C/2K Group, R8C/2L Group

16. Timers

Rev.1.10

Dec 21, 2007

Page 143 of 450

REJ09B0406-0110

16.1.3

Event Counter Mode

In event counter mode, external signal inputs to the INT1/TRAIO pin are counted (refer to Table 16.4 Event

Counter Mode Specifications).

Figure 16.7 shows the TRAIOC Register in Event Counter Mode.

Table 16.4

Event Counter Mode Specifications

Item

Specification

Count source

External signal which is input to TRAIO pin (active edge selectable by a program)

Count operations

• Decrement

• When the timer underflows, the contents of the reload register are reloaded and

the count is continued.

Divide ratio

1/(n+1)(m+1)

n: setting value of TRAPRE register, m: setting value of TRA register

Count start condition

1 (count starts) is written to the TSTART bit in the TRACR register.

Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register.

• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.

Interrupt request

generation timing

• When timer RA underflows [timer RA interrupt].

INT1/TRAIO pin

function

Count source input (INT1 interrupt input)

Read from timer

The count value can be read by reading registers TRA and TRAPRE.

Write to timer

• When registers TRAPRE and TRA are written while the count is stopped, values

are written to both the reload register and counter.

• When registers TRAPRE and TRA are written during the count, values are

written to the reload register and counter. (Refer to 16.1.1.1 Timer Write

Control during Count Operation.)

Select functions

•INT1 input polarity switch function

The TEDGSEL bit in the TRAIOC register selects the active edge of the count

source.

• Count source input pin select function

P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.

• Digital filter function

Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital filter

and select the sampling frequency.

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