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R8C2K датащи(PDF) 156 Page - Renesas Technology Corp |
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R8C2K датащи(HTML) 156 Page - Renesas Technology Corp |
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156 / 471 page ![]() R8C/2K Group, R8C/2L Group 16. Timers Rev.1.10 Dec 21, 2007 Page 139 of 450 REJ09B0406-0110 16.1.1 Timer Mode In this mode, the timer counts an internally generated count source (refer to Table 16.2 Timer Mode Specifications). Figure 16.4 shows the TRAIOC Register in Timer Mode. Figure 16.4 TRAIOC Register in Timer Mode Table 16.2 Timer Mode Specifications Item Specification Count sources f1, f2, f8, fOCO Count operations • Decrement • When the timer underflows, the contents of the reload register are reloaded and the count is continued. Divide ratio 1/(n+1)(m+1) n: Value set in TRAPRE register, m: Value set in TRA register Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register. Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register. • 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register. Interrupt request generation timing When timer RA underflows [timer RA interrupt]. INT1/TRAIO pin function Programmable I/O port, or INT1 interrupt input Read from timer The count value can be read by reading registers TRA and TRAPRE. Write to timer • When registers TRAPRE and TRA are written while the count is stopped, values are written to both the reload register and counter. • When registers TRAPRE and TRA are written during the count, values are written to the reload register and counter. (Refer to 16.1.1.1 Timer Write Control during Count Operation.) Timer RA I/O Control Register Symbol Address After Reset TRAIOC 0101h 00h Bit Symbol Bit Name Function RW INT1 _____ /TRAIO select bit 0 : INT1 _____ /TRAIO pin (P1_7) 1 : INT1 _____ /TRAIO pin (P1_5) Nothing is assigned. If necessary, set to 0. When read, the content is 0. Reserved bit TRAIO input filter select bits Set to 0 in timer mode. Set to 0. RW TRAIO polarity sw itch bit 0 TRAIO output control bit Set to 0 in timer mode. — (b7-b6) — TOPCR RW — (b2) RW RW TIPF0 RW TIPF1 00 b7 b6 b5 b4 b3 b2 TIOSEL b1 b0 0 0 TEDGSEL |
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