R8C2K datasheet(155/471 Pages) RENESAS

155 / 471 page

R8C/2K Group, R8C/2L Group

16. Timers

Rev.1.10

Dec 21, 2007

Page 138 of 450

REJ09B0406-0110

Figure 16.3

Registers TRAMR, TRAPRE, and TRA

Timer RA Mode Register

Symbol

Address

After Reset

TRAMR

0102h

00h

Bit Symbol

Bit Name

Function

NOTE:

TCK0

b3 b2

—

(b3)

b1 b0

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

—

b7 b6 b5 b4

TMOD1

TMOD0

Timer RA operating mode

select bits(1)

b2 b1 b0

0 0 0 : Timer mode

0 0 1 : Pulse output mode

0 1 0 : Event counter mode

0 1 1 : Pulse w idth measurement mode

1 0 0 : Pulse period measurement mode

1 0 1 :

1 1 0 :

Do not set.

1 1 1 :

TMOD2

When both the TSTART and TCSTF bits in the TRACR register are set to 0 (count stops), rew rite this register.

Timer RA count source

cutoff bit

0 : Provides count source

1 : Cuts off count source

TCK2

Timer RA count source

select bits

b6 b5 b4

0 0 0 : f1

0 0 1 : f8

0 1 0 : fOCO

0 1 1 : f2

1 0 0 :

1 0 1 :

Do not set.

1 1 0 :

1 1 1 :

TCKCUT

TCK1

Timer RA Prescaler Register

Symbol

Address

After Reset

TRAPRE

0103h

FFh(1)

Mode

Function

Setting Range

NOTE:

1. When the TSTOP bit in the TRACR register is set to 1, the TRAPRE register is set to FFh.

Event counter mode

Counts an external count source

00h to FFh

Measure pulse w idth of input pulses from

external (counts internal count source)

00h to FFh

Pulse period

measurement mode

Measure pulse period of input pulses from

external (counts internal count source)

Pulse output mode

00h to FFh

Counts an internal count source

00h to FFh

Pulse w idth

measurement mode

Timer mode

Timer RA Register

Symbol

Address

After Reset

TRA

0104h

FFh(1)

Mode

Function

Setting Range

NOTE:

1. When the TSTOP bit in the TRACR register is set to 1, the TRA register is set to FFh.

All modes

Counts on underflow of timer RA prescaler

00h to FFh

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