AD9958

Rev. A | Page 40 of 44

Bit

Mnemonic

Description

6

External power-down mode

0 = the external power-down mode is in fast recovery power-down mode (default). In this mode,

when the PWR_DWN_CTL input pin is high, the digital logic and the DAC digital logic are

powered down. The DAC bias circuitry, PLL, oscillator, and clock input circuitry are not powered

down.

1 = the external power-down mode is in full power-down mode. In this mode, when the

PWR_DWN_CTL input pin is high, all functions are powered down. This includes the DAC and PLL,

which take a significant amount of time to power up.

5

SYNC_CLK disable

0 = the SYNC_CLK pin is active (default).

1 = the SYNC_CLK pin assumes a static Logic 0 state (disabled). In this state, the pin drive logic is

shut down. However, the synchronization circuitry remains active internally to maintain normal

device operation.

4

DAC reference power-down

0 = DAC reference is enabled (default).

1 = DAC reference is powered down.

3:2

Open

See the Synchronizing Multiple AD9958 Devices section for details.

1

Manual hardware sync

0 = the manual hardware synchronization feature of multiple devices is inactive (default).

1 = the manual hardware synchronization feature of multiple devices is active.

0

Manual software sync

0 = the manual software synchronization feature of multiple devices is inactive (default).

1 = the manual software synchronization feature of multiple devices is active. See the

Synchronizing Multiple AD9958 Devices section for details.

Function Register 2 (FR2)—Address 0x02

Two bytes are assigned to this register. The FR2 is used to control the various functions, features, and modes of the AD9958.

Table 33. Bit Descriptions for FR2

Bit

Mnemonic

Description

15

All channels autoclear sweep

accumulator

0 = a new delta word is applied to the input, as in normal operation, but not loaded into the

accumulator (default).

1 = this bit automatically and synchronously clears (loads 0s into) the sweep accumulator for one

cycle upon reception of the I/O_UPDATE sequence indicator on both channels.

14

All channels clear

0 = the sweep accumulator functions as normal (default).

sweep accumulator

1 = the sweep accumulator memory elements for both channels are asynchronously cleared.

13

All channels autoclear phase

accumulator

0 = a new frequency tuning word is applied to the inputs of the phase accumulator, but not

loaded into the accumulator (default).

1 = this bit automatically and synchronously clears (loads 0s into) the phase accumulator for one

cycle upon receipt of the I/O update sequence indicator on both channels.

12

All channels clear phase

0 = the phase accumulator functions as normal (default).

Accumulator

1 = the phase accumulator memory elements for both channels are asynchronously cleared.

11:8

Open

7

Auto sync enable

See the Synchronizing Multiple AD9958 Devices section for more details.

6

Multidevice sync master enable

See the Synchronizing Multiple AD9958 Devices section for more details.

5

Multidevice sync status

See the Synchronizing Multiple AD9958 Devices section for more details.

4

Multidevice sync mask

See the Synchronizing Multiple AD9958 Devices section for more details.

3: 2

Open

1:0

System clock offset

See the Synchronizing Multiple AD9958 Devices section for more details.