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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HD404339FS датащи(PDF) 28 Page - Renesas Technology Corp |
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HD404339FS датащи(HTML) 28 Page - Renesas Technology Corp |
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28 / 80 page  HD404339 Series 26 Oscillator Circuit Figure 18 shows a block diagram of the clock generation circuit. The system clock frequency of the oscillator connected to OSC 1 and OSC2 can be selected by system clock selection registers 1 and 2 (SSR1, 2: $027, $028) as shown in figures 20 and 21. The system clock division ratio can be set by software to be 1/4, 1/8, 1/16, or 1/32. The subsystem clock division ratio can be set by software to be 1/4 or 1/8. OSC2 OSC1 X1 X2 System oscillator Sub- system oscillator 1/4, 1/8, 1/16, or 1/32 division circuit Timing generator circuit System clock selection CPU with ROM, RAM, registers, flags, and I/O Peripheral function interrupt Time-base interrupt Time-base clock selection 1/8 or 1/4 division circuit Timing generator circuit Timing generator circuit 1/8 division circuit fW fSUB tsubcyc LSON TMA3 fcyc tcyc fOSC fX tWcyc øCPU øPER øCLK Notes: 1. 2. The system clock division ratio can be selected by setting bit 1 or 0 of the system clock select register 2 (SSR2: $028). The system clock division ratio can be selected by setting bit 2 of the system clock select register 1 (SSR1: $027). *1 *2 Figure 18 Clock Generation Circuit |
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