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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M306V2EEFS датащи(PDF) 113 Page - Renesas Technology Corp |
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M306V2EEFS датащи(HTML) 113 Page - Renesas Technology Corp |
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113 / 271 page  Rev.1.40 Oct 06, 2004 page 113 of 269 M306V2ME-XXXFP, M306V2EEFP Figure 2.11.17 Typical transmit/receive timings in clock synchronous serial I/O mode • Example of transmit timing (when internal clock is selected) • Example of receive timing (when external clock is selected) D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Tc TCLK Stopped pulsing because transfer enable bit = “0” Data is set in UARTi transmit buffer register Tc = TCLK = 2(n + 1) / fi fi: frequency of BRGi count source (f 1, f8, f32) n: value set to BRGi Transfer clock Transmit enable bit (TE) Transmit buffer empty flag (Tl) CLKi TxDi Transmit register empty flag (TXEPT) “H” “L” “0” “1” “0” “1” “0” “1” CTSi The above timing applies to the following settings: • Internal clock is selected. • CTS function is selected. • CLK polarity select bit = “0”. • Transmit interrupt cause select bit = “0”. Transmit interrupt request bit (IR) “0” “1” Stopped pulsing because CTS = “H” 1 / fEXT Dummy data is set in UARTi transmit buffer register Transmit enable bit (TE) Transmit buffer empty flag (Tl) CLKi RxDi Receive complete flag (Rl) RTSi “H” “L” “0” “1” “0” “1” “0” “1” Receive enable bit (RE) “0” “1” Receive data is taken in Transferred from UARTi transmit buffer register to UARTi transmit register Read out from UARTi receive buffer register The above timing applies to the following settings: • External clock is selected. • RTS function is selected. • CLK polarity select bit = “0”. fEXT: frequency of external clock Transferred from UARTi receive register to UARTi receive buffer register Receive interrupt request bit (IR) “0” “1” D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 Shown in ( ) are bit symbols. Transferred from UARTi transmit buffer register to UARTi transmit register Meet the following conditions are met when the CLK input before data reception = “H” • Transmit enable bit “1” • Receive enable bit “1” • Dummy data write to UARTi transmit buffer register Shown in ( ) are bit symbols. Cleared to “0” when interrupt request is accepted, or cleared by software Cleared to “0” when interrupt request is accepted, or cleared by software |
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