6V7 datasheet(33/298 Pages) RENESAS

33 / 298 page

Rev.1.00

May 18, 2004

page 33 of 296

M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP

Table 2.4.7 Microcomputer status in hold state

Item

Status

Oscillation

___

_____

_______

R/W signal, address bus, data bus, CS, BHE

Floating

Programmable I/O ports

P0, P1, P2, P3, P4, P5

Floating

P6, P7, P8, P9, P10

Maintains status when hold signal is received

__________

HLDA

Output “L”

Internal peripheral circuits

ON (but watchdog timer stops)

ALE signal

Undefined

(6) Hold signal

The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting “L”

__________

to the HOLD pin places the microcomputer in the hold state at the end of the current bus access. This

__________

status is maintained and “L” is output from the HLDA pin as long as “L” is input to the HOLD pin. Table

2.4.7 shows the microcomputer status in the hold state.

__________

Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence.

Figure 2.4.6 Bus-using priorities

__________

HOLD > DMAC > CPU

(7) External bus status when internal area is accessed

Table 2.4.8 shows the external bus status when the internal area is accessed.

Table 2.4.8 External bus status when the internal area is accessed

(8) BCLK output

The output of the internal clock

φ can be selected using bit 7 of the processor mode register 0 (address

000416) (Note). The output is floating when bit 7 is set to “1”.

Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the

protect register (address 000A16) to “1”.

Item

SFR accessed

Internal ROM/RAM accessed

Address bus

Address output

Maintain status before accessed

address of external area

Data bus

When read

Floating

When write

Output data

Indefinite

RD, WR, WRL, WRH

RD, WR, WRL, WRH output

Indefinite

BHE

BHE output

Maintain status before accessed

status of external area

Output "H"

ALE

Indefinite

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