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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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6V7 датащи(PDF) 77 Page - Renesas Technology Corp |
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6V7 датащи(HTML) 77 Page - Renesas Technology Corp |
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77 / 298 page  Rev.1.00 May 18, 2004 page 77 of 296 M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP Single-chip mode Memory expansion mode Transfer unit Bus width Access address Microprocessor mode No. of read No. of write No. of read No. of write cycles cycles cycles cycles 16-bit Even 1 1 1 1 8-bit transfers (BYTE= “L”) Odd 1 1 1 1 (DMBIT= “1”) 8-bit Even — — 1 1 (BYTE = “H”) Odd — — 1 1 16-bit Even 1 1 1 1 16-bit transfers (BYTE = “L”) Odd 2 2 2 2 (DMBIT= “0”) 8-bit Even — — 2 2 (BYTE = “H”) Odd — — 2 2 Table 2.9.2 No. of DMAC transfer cycles 2.9.2 DMAC Transfer Cycles Any combination of even or odd transfer read and write addresses is possible. Table 2.9.2 shows the number of DMAC transfer cycles. The number of DMAC transfer cycles can be calculated as follows: No. of transfer cycles per transfer unit = No. of read cycles ✕ j + No. of write cycles ✕ k Internal memory External memory Internal ROM/RAM SFR area Separate bus Separate bus /OSD RAM No wait With wait 12 1 2 Coefficient j, k |
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