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33742 датащи(PDF) 53 Page - Freescale Semiconductor, Inc

номер детали 33742
подробное описание детали  System Basis Chip with Enhanced High Speed CAN Transceiver
PDF  70 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

33742 датащи(HTML) 53 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
Freescale Semiconductor
53
33742
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Figure 28. Window Watchdog
Figure 29. Timeout Watchdog
Table 31. TIM1 Control Bits
WDW
WDT1
WDT0
Timing (ms typ)
Parameter
Description
0
0
0
9.75
Watchdog Period 1
No Window Watchdog
0
0
1
45
Watchdog Period 2
0
1
0
100
Watchdog Period 3
0
1
1
350
Watchdog Period 4
1
0
0
9.75
Watchdog Period 1
Watchdog Window enabled
(Window length is half the
Watchdog Timing).
1
0
1
45
Watchdog Period 2
1
1
0
100
Watchdog Period 3
1
1
1
350
Watchdog Period 4
Watchdog Timing x 50%
Watchdog Timing x 50%
Watchdog Period
(Watchdog Timing Selected by TIM1 Bit WDW =1)
Window Closed
No Watchdog Clear Allowed
Window Open for Watchdog Clear
Watchdog Period
(Watchdog Timing Selected by TIM1 Bit WDW = 0)
Window Open for Watchdog Clear
Table 32. Timing Register Status Bits
Name
Logic
Failure Description
CANL2VDD
0
No CANL short to VDD.
1
CANL short to VDD.
CANL2BAT
0
No CANL short to VSUP.
1
CANL short to VSUP.
CANL2GND
0
No CANL short to GND.
1
CANL short to GND.
TXPD
0
No TXD dominant.
1
TXD dominant.
Table 33. TIM2 Timing and CANL Failure Diagnostic Register
TIM2
R/W
D3
D2
D1
D0
$101b
W
1
CSP2
CSP1
CSP0
R
CANL2VDD
CANL2BAT
CANL2GND
TXPD
Reset Value
–
–
0
0
0
Reset Condition (Write)(64)
–
–
POR, RESET
POR, RESET
POR, RESET
Notes
64.
See Table 13, page 47, for definitions of reset conditions.



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