33742 datasheet(5/70 Pages) FREESCALE

5 / 70 page

Analog Integrated Circuit Device Data

Freescale Semiconductor

33742

PIN CONNECTIONS

Figure 4. 33742 48-Pin Connections

Table 3. 33742 48-Pin Definitions

A functional description of each pin can be found in the Functional Pin description section beginning on page 23.

Pin Name

Formal Name

Definition

1, 12-16,

21-25,

36-40,

45-48

No Connect

No connection.

SCLK

Serial Data Clock

Clock input pin for the Serial Peripheral Interface (SPI).

MISO

Master In Slave Out

SPI data sent to the MCU by the 33742. When CS is HIGH, the pin is in the high-

impedance state.

MOSI

Master Out Slave In

SPI data received by the 33742.

Chip Select

(Active LOW)

The CS input pin is used with the SPI bus to select the 33742. When the CS is asserted

LOW, the 33742 is the selected device of the SPI bus.

WDOG

Watchdog Output

(Active LOW)

The WDOG output pin is asserted LOW if the software watchdog is not correctly

triggered.

RXD

Receive Data

CAN bus receive data output pin.

TXD

Transmit Data

CAN bus transmit data input pin.

VDD

Voltage Digital Drain

5.0V regulator output pin. Supply pin for the MCU.

RST

Reset Output

(Active LOW)

This is the device reset output pin whose main function is to reset the MCU. This pin has

an internal pullup current source to VDD.

INT

Interrupt Output

(Active LOW)

This output is asserted LOW when an enabled interrupt condition occurs. The output is

a push-pull structure.

17-20

41-44

GND

Ground

These device ground pins are internally connected to the package lead frame to provide

a 33742-to-PCB thermal path.

SCLK

RXD

VDD

TXD

V2 CTRL

CANH

CANL

MISO

MOSI

WDOG

INT

VSUP

RST

Transparent

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