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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STW4811MBRA/LF датащи(PDF) 20 Page - STMicroelectronics |
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STW4811MBRA/LF датащи(HTML) 20 Page - STMicroelectronics |
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20 / 86 page  STw4811M/STw4811N Functional description 19/85 4.2.2 POWER OFF / VDDOK ● In case of VDDOK falling edge due to under voltage on VCORE or VIO_VMEM detection, or ‘it_twarn’ bit set to “1” ( Table 18); the multimedia processor is then reset (PORn low during a minimum time of 333 µs) and restarted with no time-out. (see Figure 5). In case of VDDOK falling edge because PWREN balls equals “0”, there is no reset (PORn still high). ● In case of PON falling edge (STw4811 switched off from modem); the multimedia processor is also reset with no time-out. We consider that clean switch off between modem and multimedia processor is done by software directly. Figure 5. VDDOK block diagram 4.2.3 Sleep mode STw4811 goes into sleep mode by different ways. Whether VCORE, VIO_VMEM and VAUX are programmed to sleep mode or not is indicated in Table 26 and Table 27. Taking in account the bit programming from Table 26 and Table 27, sleep mode is summarized with the following formula: SLEEP = (‘vxxx_sleep’ x PWREN) + (‘vxxx_force_sleep’) = 1 (vxxx = vcore or vio_vmem or vaux) Note: The configuration vxxx_sleep = 0 (device in active mode) and vxxx_force_sleep = 1 (device in sleep mode, but no priority level on this bit) is forbidden. If the master clock is used in high power mode when switching to sleep mode, the following features are not available: – Bit 1 (vcore_sleep) and bit 2 (vio_vmem_sleep) in power control register address 9 must be at high level (VIO_VMEM and VCORE cannot remain in high power mode) – USB charge pump is not available in sleep mode: bit 5 in USB control register address 07h must be set Digital block & VDDOK it_twarn Reg status register reset after read operation or PON falling edge or PORN_VBAT. mask_twarn PWREN |
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