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SABRE-LL-I датащи(PDF) 20 Page - STMicroelectronics

номер детали SABRE-LL-I
подробное описание детали  Combo motor driver
PDF  141 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
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SABRE-LL-I датащи(HTML) 20 Page - STMicroelectronics

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Supervisory system
SABRE-LL-I
20/141
is monitored by POR, so it must be above its minimum value, otherwise nRESET circuit is
not active).
This circuit generates an internal reset signal (in the following indicated as “nRST_int”) that
will also be signaled to external circuits by pulling low the nRESET pin.
The signal nRST_int becomes active in the following cases:
1.
When one of the following voltages is lower than its own under voltage threshold:
–VSupply and VSupply_int.
–VPump.
–VSystem (all switching or linear system regulators voltages).
–VGPIO_SPI.
2.
When watchdog timer counter (see Chapter 6) elapse the watchdog timeout time (only
if watchdog function is enabled).
3.
When S.A.B.Re is in “Low Power mode”.
4.
When EnExtSoftRst bit in SoftResReg register is at logic level = “1” and a “SoftRes”
command is applied (see SoftResReg register description in Chapter 25).
When an nRST_int event is caused by above cases, the nRESET pin will stay low for a
“stretch” time that starts from the moment that nRST_int signal returns in the operative
state. This stretch time can be selected by setting the ID[1:0] bits in the SampleID register
according to following table:
When nRST_int becomes active (logic level = “0”) it sets in their reset state some of the
functions inside S.A.B.Re. The main functions that will be reset by nRST_int signal are the
following:
Serial interface will be reset and will not accept any other command.
The bridges 1 and 2 will place their outputs in high impedance and PWM and
direction signals will be reset.
Not system regulators will be powered off.
AD converter will be powered off.
GPIOs will be powered off.
Current DAC will be powered off.
Operational amplifiers will be powered off.
Watchdog count will be reset (while Watchdog flags won’t be reset).
Interrupt controller will be powered off.
Digital comparator will be powered off.
Table 8.
Stretch time selection
ID[1]
ID[0]
Selected stretch time
Note
Typ
0
0
16ms
Default state
01
32ms
10
48ms
11
64ms



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