SABRE-LL-I datasheet(77/141 Pages) STMICROELECTRONICS

77 / 141 page

SABRE-LL-I

AD converter

77/141

A conversion on channel 1 can be triggered by writing a logic ‘1’ in the A2DTrig1 bit in the

A2DConfigX register and a conversion on channel 2 can be triggered writing a logic ‘1’ in the

A2DTrig2 bit in the same register. While a request on a channel is pending but not yet

completed S.A.B.Re will force to logic ‘0’ the corresponding A2DdoneX bit in the

A2DResultX registers and S.A.B.Re will not accept other conversion request on that

channel.

Continuous conversion on one channel can be accomplished by setting to logic ‘1’ the

A2DcontinuousX bit in the A2DConfigX register. When A2DcontinuousX bit is set, other

conversions can be accomplished on the other channel; these conversions will be inserted

between two conversions of the other channel and the end of the conversion will be

signaled using A2DdoneX bit. Of course when a channel is in continuous mode its sample

time and channel address cannot be changed.

Continuous conversions on both 2 channels can be also accomplished by setting to logic ‘1’

the A2Dcontinuous1 and A2Dcontinuous2 bits; the conversions are made in sequence.

Table 53.

ADC sample times when working as a 8-bit ADC

A2DSampleX[2:0] (binary)

Sample time

Typ

Unit

000

16*Tosc

µs

001

32*Tosc

µs

010

64*Tosc

µs

011

128*Tosc

µs

100

256*Tosc

µs

101

512*Tosc

µs

110

1024*Tosc

µs

111

2048*Tosc

µs

Table 54.

ADC sample time when working as a 9-bit ADC

A2DSampleX[2:0] (binary)

Sample time

Typ

Unit

000

32*Tosc

µs

001

64*Tosc

µs

010

128*Tosc

µs

011

256*Tosc

µs

100

512*Tosc

µs

101

1024*Tosc

µs

110

2048*Tosc

µs

111

4096*Tosc

µs

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