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JS28F640P30T85 датащи(PDF) 32 Page - Numonyx B.V

номер детали JS28F640P30T85
подробное описание детали  Numonyx StrataFlash Embedded Memory
PDF  99 Pages
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производитель  NUMONYX [Numonyx B.V]
домашняя страница  http://www.numonyx.com
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P30
Datasheet
November 2007
32
Order Number: 306666-11
R301
tAVCH/L
Address setup to CLK
9
-
ns
1
R302
tVLCH/L
ADV# low setup to CLK
9
-
ns
R303
tELCH/L
CE# low setup to CLK
9
-
ns
R304
tCHQV / tCLQV
CLK to output valid
-
17
ns
R305
tCHQX
Output hold from CLK
3
-
ns
1,7
R306
tCHAX
Address hold from CLK
10
-
ns
1,4,7
R307
tCHTV
CLK to WAIT valid
-
17
ns
1,7
R311
tCHVL
CLK Valid to ADV# Setup
3
-
ns
1
R312
tCHTX
WAIT Hold from CLK
3
-
ns
1,7
Notes:
1.
See
Figure 11, “AC Input/Output Reference Waveform” on page 28 for timing measurements and max
allowable input slew rate.
2.
OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to tELQV.
3.
Sampled, not 100% tested.
4.
Address hold in synchronous burst mode is tCHAX or tVHAX, whichever timing specification is satisfied first.
5.
Please see the latest P30 Spec Update for synchronous burst operation with the TSOP package.
6.
Synchronous read mode is not supported with TTL level inputs.
7.
Applies only to subsequent synchronous reads.
Table 17: AC Read Specifications for 256/512-Mbit Densities (Sheet 3 of 3)
Num
Symbol
Parameter
Speed
Min
Max
Unit
Notes
Table 18: AC Read Specification differences for 65nm
Num
Symbol
Parameter
Min
Max
Unit
Notes
Asynchronous Specifications
R1
tAVAV
Read cycle time
100
-
ns
2
TSOP
110
ns
2
R2
tAVQV
Address to output valid
-
100
ns
2
TSOP
110
ns
2
R3
tELQV
CE# low to output valid
-
100
ns
2
TSOP
110
ns
2
R103
tVLQV
ADV# low to output valid
-
100
ns
1,2
TSOP
110
ns
2
Notes:
1.
See
Figure 11, “AC Input/Output Reference Waveform” on page 28 for timing measurements and
max allowable input slew rate.
2.
This is the recommended specification for all new designs supporting both 130nm and 65nm lithos, or for new designs
that will use the 65nm lithography.



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