JS28F640P30T85 datasheet(8/99 Pages) NUMONYX

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P30

Datasheet

November 2007

Order Number: 306666-11

2.0

Functional Overview

This section provides an overview of the features and capabilities of the P30.

The P30 family provides density upgrades from 64-Mbit through 512-Mbit. This family

of devices provides high performance at low voltage on a 16-bit data bus. Individually

erasable memory blocks are sized for optimum code and data storage.

Upon initial power up or return from reset, the device defaults to asynchronous page-

mode read. Configuring the Read Configuration Register enables synchronous burst-

mode reads. In synchronous burst mode, output data is synchronized with a user-

supplied clock signal. A WAIT signal provides an easy CPU-to-flash memory

synchronization.

In addition to the enhanced architecture and interface, the device incorporates

technology that enables fast factory program and erase operations. Designed for low-

voltage systems, the

P30 supports read operations with VCC at 1.8 V, and erase and program operations with

VPP at 1.8 V or 9.0 V. Buffered Enhanced Factory Programming (BEFP) provides the

fastest flash array programming performance with VPP at 9.0 V, which increases factory

throughput. With VPP at 1.8 V, VCC and VPP can be tied together for a simple, ultra low

power design. In addition to voltage flexibility, a dedicated VPP connection provides

complete data protection when VPP ≤ VPPLK.

A Command User Interface (CUI) is the interface between the system processor and all

internal operations of the device. An internal Write State Machine (WSM) automatically

executes the algorithms and timings necessary for block erase and program. A Status

An industry-standard command sequence invokes program and erase automation. Each

erase operation erases one block. The Erase Suspend feature allows system software to

pause an erase cycle to read or program data in another block. Program Suspend

allows system software to pause programming to read other locations. Data is

programmed in word increments (16 bits).

The P30 protection register allows unique flash device identification that can be used to

increase system security. The individual Block Lock feature provides zero-latency block

locking and unlocking. In addition, the P30 device also has four pre-defined spaces in

the main array that can be configured as One-Time Programmable (OTP).

2.1

Virtual Chip Enable Description

The P30 512Mbit devices employ a Virtual Chip Enable which combines two 256-Mbit

die with a common chip enable, F1-CE# for QUAD+ packages or CE# for Easy BGA and

TSOP packages. (Refer to Figure 9 on page 21 and Figure 10 on page 21). Address A24

(Quad+ package) or A25 (Easy BGA and TSOP packages) is then used to select

between the die pair with F1-CE# / CE# asserted depending upon the package option

used. When chip enable is asserted and QUAD+ A24 (Easy BGA/TSOP A25) is low (VIL),

The lower parameter die is selected; when chip enable is asserted and QUAD+ A24

(Easy BGA/TSOP A25) is high (VIH), the upper parameter die is selected. Refer to

Table 1 and Table 2 for additional details.

Table 1:

Virtual Chip Enable Truth Table for 512 Mb (QUAD+ Package)

Die Selected

F1-CE#

A24

Lower Param Die

Upper Param Die

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