IMX27L datasheet(8/122 Pages) FREESCALE

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i.MX27/iMX27L Data Sheet, Advance Information, Rev. 1

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

Functional Description and Application Information

SAHARA2

Symmetric/

Asymmetric

Hashing and

Random

Accelerator

Security

SAHARA2 is a security co-processor which forms part of the

Platform Independent Security Architecture (PISA), and can be

used on cell phone baseband processors or wireless PDAs.

2.3.30/21

SCC

Security

Controller

Module

Security

The SCC is a hardware component composed of two

blocks—the Secure RAM module, and the Security Monitor.

The Secure RAM provides a way of securely storing sensitive

information. The Security Monitor implements the security

policy, checking algorithm sequencing, and controlling the

Secure State.

2.3.31/22

SDHC

SecuredDigital

Host Controller

Connectivity

Peripheral

The SDHC controls the MMC (MultiMediaCard), SD (Secure

Digital) memory, and I/O cards by sending commands to cards

and performing data accesses to and from the cards.

2.3.32/22

SLCDC

Smart Liquid

Crystal Display

Controller

Multimedia

Interface

The SLCDC module transfers data from the display memory

buffer to the external display device.

2.3.33/23

SSI

Synchronous

Serial Interface

Multimedia

Peripheral

The SSI is a full-duplex, serial port that allows the chip to

communicate with a variety of serial devices, such as standard

codecs, digital signal processors (DSPs), microprocessors,

peripherals, and popular industry audio codecs that implement

the inter-IC sound bus standard (I2S) and Intel AC97 standard.

2.3.34/23

UART

Universal

Asynchronous

Receiver/

Transmitter

Connectivity

Peripheral

The UART provides serial communication capability with

external devices through an RS-232 cable or through use of

external circuitry that converts infrared signals to electrical

signals (for reception) or transforms electrical signals to signals

that drive an infrared LED (for transmission) to provide low

speed IrDA compatibility.

2.3.35/24

USB

Universal

Serial Bus–2

Host

Controllers

and 1 OTG

(On-The-Go)

Connectivity

Peripherals

The i.MX27/MX27L processors provide two USB Host

controllers and one USBOTG of which:

• USB Host 1 is designed to support transceiverless

connection to the on-board peripherals in Low Speed and

Full Speed mode, and connection to the ULPI

(UTMI+Low-Pin Court) and Legacy Full Speed transceivers

• USB Host 2 is designed to support transceiverless

connection to the Cellular Modem Baseband Processor

• The USBOTG controller offers HS/FS/LS capabilities in

Host mode and HS/FS in device mode. In Host mode, the

controller supports direct connection of a FS/LS device

(without external hub). In device (bypass) mode, the OTG

port functions as gateway between the Host 1 Port and the

OTG transceiver.

2.3.36/24

Video Codec

Hardware

Acceleration

Video Codec module supports full duplex video codec with 25

fps VGA image resolution, integrates H.264 BP, MPEG-4 SP

and H.263 P3 video processing standard together.

Note:

This feature is not available on MX27L.

2.3.39/26

Table 2. Digital and Analog Modules (continued)

Block Mnemonic

Block Name

Functional

Grouping

Brief Description

Section/

Page

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