IMX27L datasheet(21/122 Pages) FREESCALE

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Functional Description and Application Information

i.MX27/i.MX27L Data Sheet, Advance Information, Rev. 1

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

•

Once-per-day, once-per-hour, once-per-minute, and once-per-second interrupts

•

Operation at 32.768 kHz or 32 kHz, or 38.4 kHz (determined by reference clock crystal)

The prescaler converts the incoming crystal reference clock to a 1 Hz signal, which is used to increment

the seconds, minutes, hours, and days TOD counters. The alarm functions, when enabled, generate RTC

interrupts when the TOD settings reach programmed values. The sampling timer generates

fixed-frequency interrupts, and the minute stopwatch allows for efficient interrupts on very small

boundaries.

2.3.29

Run-TIme Integrity Checker (RTIC)

The run-time integrity checker (RTIC) is one of the security components in the i.MX27/MX27L

processors. Its purpose is to ensure the integrity of the peripheral memory contents and assist with boot

authentication. The RTIC has the ability to verify the memory contents during system boot and during

run-time execution. If the memory contents at runtime fail to match the hash signature, an error in the

security monitor is triggered.

The RTIC provides SHA-1 message authentication and receives input via the DMA (AMBA-AHB Lite

bus master) interface. It uses segmented data gathering to support non-contiguous data blocks in memory

(up to two segments per block) and works during and with high assurance boot (HAB) process. It provides

Secure-scan DFT security and support for up to four independent memory blocks. The RTIC has both a

Programmable DMA bus duty cycle timer and its own watchdog timer.

The RTIC operates in two primary modes:

•

One-time hash mode—One-time hash mode is used during HAB for code authentication or

one-time integrity checking, during which it stores the hash result internally and signals the

ARM926 using an interrupt.

•

Continuous-hash mode—In continuous-hash mode, the RTIC is used continuously to verify

integrity of memory contents by checking re-generated hash against internally stored values and

interrupts host only if error occurs.

2.3.30

Symmetric/Asymmetric Hashing and Random Accelerator

(SAHARA2)

SAHARA2 is a security co-processor and implements encryption algorithms (AES, DES, and 3DES),

hashing algorithms (MD5, SHA-1, SHA_224, and SHA-256), stream cipher algorithm (ARC4), and a

hardware random number generator.

SAHARA2 offer features:

•

AES encryption/decryption

— ECB, CBC, CTR, and CRM modes

— 128-bit key

•DES/3DES

— EBC, CBC, and CTR modes

— 56-bit key with parity (DES)

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