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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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IMX27L датащи(PDF) 76 Page - Freescale Semiconductor, Inc |
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IMX27L датащи(HTML) 76 Page - Freescale Semiconductor, Inc |
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76 / 122 page  i.MX27/iMX27L Data Sheet, Advance Information, Rev. 1 76 Preliminary—Subject to Change Without Notice Freescale Semiconductor Signal Descriptions NOTE SDR SDRAM CLK parameters are being measured from the 50% point—that is, high is defined as 50% of signal value and low is defined as 50% of signal value. SD1 + SD2 does not exceed 7.5 ns for 133 MHz. The timing parameters are similar to the ones used in SDRAM data sheets—that is, Table 36 indicates SDRAM requirements. All output signals are driven by the ESDCTL at the negative edge of SDCLK and the parameters are measured at maximum memory frequency. SD6 Address setup time tAS 2.0 — ns SD7 Address hold time tAH 1.8 — ns SD8 SDRAM access time tAC — 6.47 ns SD9 Data out hold time1 tOH 1.8 — ns SD10 Active to read/write command period tRC 10 — clock 1 Timing parameters are relevant only to SDR SDRAM. For the specific DDR SDRAM data related timing parameters, see Table 40 and Table 41. Table 36. DDR/SDR SDRAM Read Cycle Timing Parameters (continued) ID Parameter Symbol Min Max Unit |
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