A4935 datasheet(19/24 Pages) ALLEGRO

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Automotive 3-Phase MOSFET Driver

A4935

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

tor (>1000 nF). If the bootstrap capacitor voltage does not reach

the threshold within approximately 200 μs, an undervoltage fault

will be flagged.

VREG Capacitor Selection

The internal reference, VREG, supplies current for the low-side

gate drive circuits and the charging current for the bootstrap

capacitors. When a low-side FET is turned on, the gate-drive

circuit will provide the high transient current to the gate that is

necessary to turn on the FET quickly. This current, which can be

several hundred milliamperes, cannot be provided directly by the

limited output of the VREG regulator, and must be supplied by an

external capacitor connected to VREG.

The turn-on current for the high-side FET is similar in value to

that for the low-side FET, but is mainly supplied by the boot-

strap capacitor. However the bootstrap capacitor must then be

recharged from the VREG regulator output. Unfortunately the

bootstrap recharge can occur a very short time after the low-

side turn-on occurs. This requires that the value of the capacitor

connected between VREG and AGND should be high enough to

minimize the transient voltage drop on VREG for the combina-

tion of a low-side FET turn-on and a bootstrap capacitor recharge.

A value of 20 × CBOOT is a reasonable value. The maximum

working voltage will never exceed VREG, so the capacitor can be

rated as low as 15 V. This capacitor should be placed as close as

possible to the VREG pin.

Supply Decoupling

Because this is a switching circuit, there are current spikes from all

supplies at the switching points. As with all such circuits, the power

supply connections should be decoupled with a ceramic capacitor,

typically 100 nF, between the supply pin and ground. These capaci-

tors should be connected as close as possible to the device supply

pins VBB and VDD, and the power ground pin, PGND.

Power Dissipation

In applications where a high ambient temperature is expected, the

on-chip power dissipation may become a critical factor. Careful

attention should be paid to ensure the operating conditions allow

the A4935 to remain in a safe range of junction temperature.

The power consumed by the A4935, PD, can be estimated by:

PBIAS + PCPUMP + PSWITCHING ,

(6)

given:

PBIAS

VBB × IBB ;

(7)

PCPUMP

[( 2 VBB)– VREG] IAV

, for VBB <15 V,

[VBB – VREG] IAV

, for VBB ≥ 15 V,

(8)

PSWITCHING

QGATE × VREG × N × fPWM × Ratio ;

(9)

where:

IAV

QGATE × N × fPWM ,

N is the number of FETs switching during a PWM cycle, and

Ratio

RGATE + 10

Braking

The A4935 can be used to perform dynamic braking by either

forcing all low-side FETs on and all high-side FETs off or, con-

versely, by forcing all low-side FETs off and all high-side FETs

on. This will effectively short-circuit the back EMF of the motor,

creating a breaking torque.

During braking, the load current can be approximated by:

VBEMF

IBRAKE =

(10)

where VBEMF is the voltage generated by the motor and RL is the

resistance of the phase winding.

Care must be taken during braking to ensure that the maximum

ratings of the power FETs are not exceeded. Dynamic braking is

equivalent to slow decay with synchronous rectification and all

phases enabled.

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