A4935 datasheet(14/24 Pages) ALLEGRO

14 / 24 page

Automotive 3-Phase MOSFET Driver

A4935

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Fault Register

All undervoltage and short faults are recorded in a 10-bit fault

detected faults until cleared by setting RESET low, by cycling the

power off and on, or by reading the contents. The contents will

also be cleared if a VDD undervoltage fault is detected. During a

VDD undervoltage fault condition, both fault flags will be high

but all the bits in the fault register will be reset.

Table 3. Fault Register Bit Definitions

Bit

Position

Function

First

VDS exceeded on A phase high-side FET

VDS exceeded on B phase high-side FET

VDS exceeded on C phase high-side FET

VDS exceeded on A phase low-side FET

VDS exceeded on B phase low-side FET

VDS exceeded on C phase low-side FET

Undervoltage detected on VREG

Bootstrap undervoltage detected on phase A

Bootstrap undervoltage detected on phase B

Last

Bootstrap undervoltage detected on phase C

The contents of the fault register can be read serially from the

FF1 pin by applying a clock signal to the FF2 pin during an

undervoltage or short fault state.

The fault flag pins, FF1 and FF2, are open drain outputs and pas-

sively pulled high when a fault is present. This makes it possible

to drive one or both of these fault pins from an external source

during a fault condition, when the A4935 is not pulling the pin

low. FF2 can thus be used as a clock input to shift out the fault

status register, bit-by-bit, on the other fault flag, FF1.

When FF2 is being pulled low by the A4935, either when no fault

is present or when an overtemperature fault is present, then no

serial access is possible. The fault status register can be accessed

only when FF2 goes high. This occurs when either a short or an

undervoltage fault has been detected.

Faut Register Serial Access

To access the fault register, FF1 and FF2 must be monitored by

an external controller. If FF2 goes high and FF1 remains low,

then a short has been detected. If FF1 and FF2 go high together,

then an under voltage has been detected. In either case, the

sequence for reading the contents of the fault register is:

1. The external controller takes any necessary additional action to

protect the FETs.

2. The external controller pulls FF2 low.

3. The A4935 outputs on FF1 the fault register first bit, AH.

4. The external controller reads the fault bit, and then cycles FF2

high then low for the next bit, BH.

5. Steps 3 and 4 alternate until all of the 10 bits in the fault regis-

ter have been read out.

6. After the final bit, VC, is output, the external controller cycles

FF2 high then low.

7. The A4935 resets the fault register and pulls FF1 and FF2 low

to indicate no fault present.

8. The external controller releases FF2.

The basic sequence for the three possible states of FF1 and FF2

are shown in figure 1.

At the end of the serial transfer, on the last high-to-low transition

input to FF2, the fault register and the fault flags are reset. How-

ever, it is possible that one of the three unlatched fault conditions,

VREG undervoltage, VDD undervoltage, or overtemperature, is

still present. In this case the fault flags will immediately show the

fault status.

Resetting the VR Bit

At power-up, on coming out of reset, or after a VDD or VREG

undervoltage fault, it is possible that the fault flags and fault reg-

ister will have cleared but the VR bit in the fault register remains

set. This would happen if, when a power-on-reset occurred,

VREG had not yet risen beyond the undervoltage threshold level,

VREGUVon. Although VREG undervoltage fault state is not latched

and the fault flags are cleared when the fault is removed, the

VR bit in the fault register is latched and may remain set after

the power-on-reset. For this reason it is recommended, when the

serial fault register is to be used, to perform a reset by taking the

RESET pin low for less than the reset pulse time, tRES, after the

A4935 is powered-up and all fault flags are clear (FF1 and FF2

are low).

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