ST52T301 datasheet(42/100 Pages) STMICROELECTRONICS

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Bit

Name

Value

Description

0TE

Transmission DISABLED

Transmission ENABLED

1RE

Receiver DISABLED

Receiver ENABLED

8, No Parity, 1 bit stop

8, No Parity, 2 bit stop

8, Parity, 1 bit stop

9, No Parity, 1 bit stop

4T8

Parity Odd, if Parity is

selected (M

= 10); otherwise

9th Data bit

Parity Even, if Parity is

selected (M = 10); otherwise

9th Data bit

BRSL

000

600 Hz

001

1200 Hz

010

2400 Hz

011

4800 Hz

100

9600 Hz

101

19200 Hz

110

38400 Hz

111

External Clock

Table 9.1 Configuration Register 3 Setting

the START condition,the Noise error and the Frame

error.

When the SCI Receiver is in IDLE status, it is

waiting for the START condition, that is obtained

with a logic level 0, consecutive to a logic level 1.

This condition is detected,if,with thefixed sampling

time, three logic levels 0 are sampled after three

logic levels 1.

The recognition of the START bit forces the SCI

Receiver Block to enter in an data acquisition

sequence, according to serial mode.

The 2 bits, M, of the ConfigurationRegister 3 allow

to definethe serial mode with the conventionshown

in table 9.2.

The bit, T8, in case of M

= 10is used to setthe parity

check to perform, as indicated in the previous table

9.2.

The recognition of STOP condition allows to

transfer the received data, from Recovery Bufferto

SCDR_RX buffer, adding the eventual ninth data

bit, according to the meaning shown in the previous

table 9.2. After this operation, RXF flag of SCI

Status Input Register 8 (fig. 9.3) is set to logic level

1. The Control Unit reads the data from SCDR_RX

buffer (in read-only mode) with SRX instruction

and provides a reset at logic level 0 to RDRF flag.

If a data of Recovery Buffer is ready to be

transferred into SCDR_RX buffer, but the previous

one was not yet read by the Core, an OVERRUN

Error takes place: the status flag OVERR indicates

the error condition. In this case the information

stored in SCDR_RX buffer is not altered, but the

one that has caused the OVERRUN error can be

overwritten by a new data coming from the serial

data line.

Recovery Buffer Block

This block is structured as a synchronised finite

state machine on the CLOCK_RX signal falling

edge.

When the Recovery Buffer Block is in IDLE state it

waits for the reception of the correct 1 and 0

sequence representing the START.

The recognition takes place by sampling the input

RxD at CLOCK_RX f requency, that has a

frequency 16 times higher than CLOCK_TX. For

this reason, while the external transmitter sends a

single bit, the Recovery Buffer Block samples 16

states (from SAMPLE1 to SAMPLE16).

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ST52T301/E301

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