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ST52T301 датащи(PDF) 35 Page - STMicroelectronics

номер детали ST52T301
подробное описание детали  8-Bit OTP/EPROM DuaLogic] MCUs WITH ADC, UART, TIMER, TRIAC & PWM DRIVER
PDF  100 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST52T301 датащи(HTML) 35 Page - STMicroelectronics

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Bit
Name
Value
Description
0
INTSL
0
INT_TMR on Falling Edge of
Counter Stop
1
INT_TMR on Edges of
TIMEROUT
1
INTF
0
NO INT_TMR on Falling
Edge of TIMEROUT
1
INT_TMR on Falling Edge of
TIMEROUT
2
INTR
0
NO INT_TMR on Rising
Edge of TIMEROUT
1
INT_TMR on Rising Edge of
TIMEROUT
3
INPSL
0
Timer Data Input coming
from the Fuzzy Core
1
Timer Data Input coming
from a Register File location
4
FZSL
0
Timer Data Input coming
from FUZZY_OUT_0
1
Timer Data Input coming
from FUZZY_OUT_1
5
not used
-
6
not used
-
7
not used
-
Table 7.3. Configuration Register 7 Description
D7 D6 D5 D4 D3 D2 D1 D0
REG_CONF7
Timer
INTSL
- Interrupt Generator Selector
INTF
- Interrupt on TIMEROUT Falling Edge
INTR
- Interrupt on TIMEROUT Rising Edge
INPSL
- Input Data Selector
FZSL
- Fuzzy Input Selector
not used
not used
not used
Figure 7.7. Timer Configuration Register 7
CONF_REG7:
INTSL
It allows to select the interrupt mode for
the Timer.
INTSL=”0” Interrupt is generated on the
falling edge of the Counter Stop.
INTSL=”1” the interrupt is generated on
the edges of TIMEROUT.
INTF
INTR
INPSL
selects the source of the value of the
Counter between a location of the Regis-
ter File and the Fuzzy Core.
INPSL=”0”, Counter value coming from
the FC.
INPSL=”1”, Counter value coming from
the RF.
FZSL
FZSL= ”0”, the valueof the TimerCounter
is equal to FUZZY_OUT_0
FZSL= ”1”, the valueof the TimerCounter
is equal to FUZZY_OUT_1
35/99
ST52T301/E301



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