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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST20-GP1 датащи(PDF) 108 Page - STMicroelectronics |
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ST20-GP1 датащи(HTML) 108 Page - STMicroelectronics |
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108 / 116 page  ST20-GP1 108/116 ® 19.5.2 Valid/Ack protocol In this mode the two control pins PlinknotReq (Qack/Ivalid) and PlinknotAck (Qvalid/Iack) are active high. The initial (inactive) state of the two control wires is low. Figure 19.7 Byte-wide parallel port timings when using the Valid/Ack protocol Symbol Parameter Min Max Units PLink is output tPAHPRH PlinknotAck rising transition to PlinknotReq rising 0 ns tDOVPAH PlinkData0-7 setup time before rising edge of PlinknotAck 0ns tPRHPAL PlinknotReq rising edge to PlinknotAck falling edge 0 ns tPALPRL PlinknotReq falling edge after PlinknotAck falling edge 0 ns tPRLDOX PlinkData0-7 hold time after PlinknotReq falling edge (i.e. before new data may be put onto bus) 0ns PLink is input tDIVPRH PlinkData setup time before PlinknotReq rising edge 0 ns tPAHDIX PlinkData hold after PlinknotAck rising edge 0 ns tPAHPRL PlinknotReq falling edge after PlinknotAck rising edge 0 ns tPRLPAH PlinknotReq falling edge to PlinknotAck rising edge 0 ns tPRLPAL PlinknotAck falling edge after PlinknotReq falling edge 40 300 ns tPALPRH PlinknotReq rising edge after PlinknotAck falling edge 0 ns Table 19.6 Timings for Valid/Ack protocol ST20 Output PlinknotAck PlinknotReq PlinkData0-7 tDOVPAH tPAHPRH tPRLPAH tPAHDIX ST20 Input PlinknotReq PlinknotAck PlinkData0-7 tPALPRH tPAHPRL tPRLPAL valid data old data tPALPRL tDOVPRH tPRHPAL tPRLDOX (Qvalid) (Qack) (Ivalid) (Iack) |
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