ST20-GP1 datasheet(107/116 Pages) STMICROELECTRONICS

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ST20-GP1

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19.5 Parallel port timings

19.5.1 Dreq/Dack protocol

In this mode the two control pins PlinknotReq (Dreq) and PlinknotAck (Dack) are active low. The

initial (inactive) state of the two control wires is high.

Notes:

This will be a maximum of 200 ns if the port is already programmed either to accept another

byte or to write another byte and the port has the data available. In the extreme case for a

PLink output this value could be very large if the link has to wait for other external accesses

to complete before it can read the data to write out through the PLink.

Figure 19.6 Byte-wide parallel port timings when using the Dreq/Dack protocol

Symbol Parameter

Min

Max

Units

PLink is output tPALPDV

PlinknotAck falling transition to PlinkData valid

100

tPAHDOX PlinkData hold time after rising edge of PlinknotAck

tPAHDOZ PlinkData output tristate time from PlinknotAck rising edge

PLink is input

tPAHDIX

PlinkData hold after PlinknotAck rising edge

tPALDIV

PlinkData valid after PlinknotAck falling edge

PLink is input

or output

tPAHPRL

PlinknotAck rising edge to succeeding PlinknotReq falling edge

tPALPAH

PlinknotAck low time

340

tPRLPAL

Time between the input PlinknotReq falling and the output Plin-

knotAck falling

see

note 1

Table 19.5 Timings for Dreq/Dack protocol

PlinknotReq

PlinknotAck

PlinkData0-7

tPALDOV

tPALPAH

tPAHDOX

tPRLPAL

PlinkData0-7

tPAHDOZ

tPAHPRL

(Dreq)

(Dack)

tPALDIV

tPAHDIX

(Output)

(Input)

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