ST20-GP1 datasheet(50/116 Pages) STMICROELECTRONICS

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ST20-GP1

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Programmable memory interface

The ST20-GP1 programmable memory interface provides glueless support for up to four banks of

SRAM or ROM memory. Sufﬁcient conﬁguration options are provided to enable the interface to be

used with a wide variety of SRAM speeds, permitting systems to be built with optimum price/

performance trade-offs.

Although designed primarily for SRAM-like memory devices, the conﬁgurability enables glueless

connection to other peripheral devices such as FIFOs and UARTs.

The programmable memory interface is also referred to as the external memory interface (EMI).

The EMI provides conﬁguration information for four independent banks of external memory

devices. The addresses of these bank boundaries are hard wired to give each bank one quarter of

the address space of the machine. Bank 0 occupies the lowest quarter of the [signed] address

space, bank 3 is the highest, see Figure 9.1. Each bank can contain up to 1 Mbyte of external

memory.

Figure 9.1 Memory allocation

00000000

7FFFFFFF

FFFFFFFF

80000000

Internal SRAM

BFFFFFFF

C0000000

3FFFFFFF

40000000

On-chip peripheral registers (including the EMI

conﬁguration registers) are mapped into the upper

half of this bank.

Addresses shown are physical addresses.

On-chip peripheral

Subsystem

channels

Traps/

exceptions

Internal

SRAM

20000000

1FFFFFFF

registers

80000000

MemStart

80000FFF

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