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ST10R272L датащи(PDF) 61 Page - STMicroelectronics |
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ST10R272L датащи(HTML) 61 Page - STMicroelectronics |
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61 / 77 page ![]() 61/77 ST10R272L - ELECTRICAL CHARACTERISTICS Data hold after RdCS t51 SR 0 –0 – ns Data float after RdCS (with RW-delay)1 2 t53 SR – 13 + tF + 2tA 2 –2TCL - 7 + tF + 2tA 2 ns Data float after RdCS (no RW-delay)1 2 t68 SR – 3 + tF+ 2tA 2 –TCL - 7 + tF + 2tA 2 ns Address hold after RdCS, WrCS t55 CC -5 + tF – -5 + tF –ns Data hold after WrCS t57 CC 3 + tF – TCL - 7 + tF –ns 1) Output loading is specified using Figure 13 with CL = 5 pF. 2) This delay assumes that the following bus cycle is a demultiplexed bus cycle and that the data bus will only be driven externally when the RD or RdCs signal becomes active. RW- delay and t A refer to the following bus cycle. If the following bus cycle is a muxtiplexed bus cycle, refer to equivalent multiplexed AC timing (which are still applicable due to automatic insertion an idle state (2TCL) when switching from Demultiplexed to Multiplexed Bus Mode. Parameter Symbol Max CPU Clock 50MHz Variable CPU Clock 1/2TCL = 1 to 50 MHz min. max. min. max. Table 18 Demultiplexed bus 1 |
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