HT46R46 datasheet(30/77 Pages) HOLTEK

30 / 77 page

HT46R46/C46/R47/C47/R48A/C48A/R49

Rev. 1.30

June 5, 2008

The following timing diagram shows graphically the various stages involved in an analog to digital conversion process

and its associated timing.

The setting up and operation of the A/D converter func-

tion is fully under the control of the application program as

there are no configuration options associated with the

A/D converter. After an A/D conversion process has been

initiated by the application program, the microcontroller

internal hardware will begin to carry out the conversion,

during which time the program can continue with other

functions. The time taken for the A/D conversion is de-

pendent upon the device chosen and is a function of the

A/D clock period tAD as shown in the table.

Device

A/D Conversion Time

HT46R46

64tAD

Other Devices

76tAD

A/D Conversion Time

Programming Considerations

When programming, special attention must be given to

the A/D channel selection bits in the ADCR register. If

these bits are all cleared to zero no external pins will be

selected for use as A/D input pins allowing the pins to be

used as normal I/O pins. When this happens the power

supplied to the internal A/D circuitry will be reduced re-

sulting in a reduction of supply current. This ability to re-

duce power by turning off the internal A/D function by

clearing the A/D channel selection bits may be an impor-

tant consideration in battery powered applications.

Another important programming consideration is that

when the A/D channel selection bits change value the

A/D converter must be re-initialised. This is achieved by

pulsing the START bit in the ADCR register immediately

after the channel selection bits have changed state. The

exception to this is where the channel selection bits are

all cleared, in which case the A/D converter is not re-

quired to be re-initialised.

0 0 0 B

0 1 1 B

0 1 0 B

S T A R T

E O C B

P C R 2 ~

P C R 0

A C S 2 ~

A C S 0

P o w e r - o n

R e s e t

E n d o f A / D

c o n v e r s i o n

1 : D e f i n e P B c o n f i g u r a t i o n

2 : S e l e c t a n a l o g c h a n n e l

S t a r t o f A / D

c o n v e r s i o n

R e s e t A / D

c o n v e r t e r

0 0 0 B

S t a r t o f A / D

c o n v e r s i o n

R e s e t A / D

c o n v e r t e r

0 0 0 B

1 . P B p o r t s e t u p a s I / O s

2 . A / D c o n v e r t e r i s p o w e r e d o f f

t o r e d u c e p o w e r c o n s u m p t i o n

1 0 0 B

0 0 1 B

S t a r t o f A / D

c o n v e r s i o n

R e s e t A / D

c o n v e r t e r

D o n ' t c a r e

E n d o f A / D

c o n v e r s i o n

E n d o f A / D

c o n v e r s i o n

S T A R T b i t s e t h i g h w i t h i n o n e t o t e n i n s t r u c t i o n c y c l e s a f t e r t h e P C R 0 ~ P C R 2 b i t s c h a n g e s t a t e

A / D c l o c k m u s t b e f S Y S / 2 , f S Y S / 8 o r f S Y S / 3 2

N o t e :

A / D s a m p l i n g t i m e

3 2 t A D

t A D C

A / D c o n v e r s i o n t i m e

t A D C

A/D Conversion Timing

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