CMV8000 datasheet(33/90 Pages) AMSOSRAM

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CMV8000

Functional Description

Preliminary Datasheet

• PUBLIC

DS000609

• v1-00 • 2019-Jun-12

│ 32

Figure 29 shows the timing of the DVAL, LVAL and FVAL codes for the read-out of a frame of 2 rows.

This example uses the default mode of 16 LVDS outputs in 10-bit mode.

Figure 29:

Sync Code Timing in 16-Channel Mode

When only 8-channels are used, the line read-out time is 2 times longer. The control channel

considers this and adjusts the sync codes (LVAL) to suit the slower read-out. The timing extrapolates

identically for 4 and 2 channel read-out.

Attention

At the end of the frame, the DVAL signals last falling edge will occur 5 OUT_CLK cycles before the

FVAL and LVAL signals. As the pixel data is sent out at double data rate, this time is equivalent to

one 10-bit word of pixel data. The actual end of valid image data only occurs at the falling edge of

LVAL and FVAL.

Figure 30:

Sync Code Timing in 8-Channel Mode

The following diagram shows in more detail what happens on the control channel when reading out an

image. Two frames are exposed and read out through 16 data channels in 10-bit mode. The DVAL,

LVAL and FVAL pulses show when the data is valid for one 112-pixel burst, one row and one frame

respectively, while the SLOT and ROW pulses signify the overhead periods between bursts and rows.

On the last line, the status of all signals on the control channel is presented in binary format as it is

transmitted on the LVDS channel.

DATA_OUT IDLE

112

IDLE

DVAL

LVAL

FVAL

DATA_OUT IDLE

112

IDLE

DVAL

LVAL

FVAL

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