CMV8000 datasheet(30/90 Pages) AMSOSRAM

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CMV8000

Functional Description

Preliminary Datasheet

• PUBLIC

DS000609

• v1-00 • 2019-Jun-12

│ 29

Figure 25:

Request for 2 Frames in External Exposure Mode

7.3

Sensor Read-Out Format

7.3.1

LVDS Outputs

The CMV8000 has Low Voltage Differential Signaling (LVDS) outputs to transport the image data to

the surrounding system. Next to 16 data channels carrying image data, the sensor has two additional

LVDS channels dedicated to sync codes and a Double Data Rate (DDR) clock for sampling. In total,

the sensor has 18 LVDS output pairs.

The sensor uses a total of 36 pins for the LVDS outputs. Please refer to the pin list for the pin numbers

that assigned to LVDS signaling.

The 16 data channels transfer 10-bit or 12-bit pixel data from the sensor to the receiver, with each

pixel value serialized over a single LVDS pair.

The output clock channel OUT_CLK conveys a clock signal, synchronous to the data on the other

LVDS channels. It is strongly advised that this clock is used to sample the data instead of an external

clock signal. This clock has a double data rate, which means that the pixel data is launched on both

rising and falling edges of this signal. When the OUT_CLK is a 300 MHz signal, the output data rate

per channel is 600 Mbps.

The control channel puts out sync codes that contain status information of the data channels. This

information is grouped in 10-bit or 12-bit words that are sent out synchronous to the 16 data channels.

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