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©2014-2025 Renesas Electronics Corporation

December 15, 2025

General Description

The 9DMU0141 is a member of Renesas' SOC-Friendly

1.5V Ultra-Low-Power (ULP) PCIe Gen1-2-3 family. It has

integrated output terminations providing Zo = 100ohms for

direct connection to 100ohm transmission lines. The output

has an OE# pin for optimal system control and power

management. The part provides asynchronous or

glitch-free switching modes.

Recommended Application

2:1 1.5V PCIe Gen1-2-3 Clock Mux

Output Features

• 1 – Low-Power (LP) HCSL DIF pair w/Zo=100

Key Specifications

• DIF additive cycle-to-cycle jitter < 5ps

• DIF phase jitter is PCIe Gen1-2-3 compliant

• 125MHz additive phase jitter 535fs RMS typical (12kHz

to 20MHz)

Features/Benefits

• LP-HCSL output w/integrated terminations; saves 4

resistors compared to standard HCSL output

• 1.5V operation; 11mW typical power consumption

• Selectable asynchronous or glitch-free switching; allows

the mux to be selected at power up even if both inputs

are not running, then transition to glitch-free switching

mode

• Spread Spectrum Compatible; supports EMI reduction

• OE# pins; support DIF power management

• HCSL differential inputs; can be driven by common clock

sources

• 1MHz to 167MHz operating frequency

• Space saving 16-pin 3 x 3mm VFQFPN; minimal board

space

Block Diagram

A

B

DIF0

^OE0#

DIF_INA

DIF_INB

vSW_MODE

^SEL_A_B#

2:1 1.5V PCIe Gen1/2/3 Clock Mux

with Zo = 100ohms

9DMU0141

Datasheet