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©2014-2025 Renesas Electronics Corporation

December 15, 2025

9DMU0141 Datasheet

Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics

Electrical Characteristics–Phase Jitter Parameters

TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

NOTES

Duty Cycle Distortion

tDCD

Measured differentially @100MHz

-1

-0.2

1

%

1,3

Skew, Input to Output

tpdBYP

Bypass Mode, VT = 50%

2196

2923

3978

ps

1

Skew, Output to Output

tsk3

VT = 50%

N/A

N/A

ps

1

Jitter, Cycle to cycle

tjcyc-cyc

Additive Jitter

0.1

8

ps

1,2

1 Guaranteed by design and characterization, not 100% tested in production.

2 Measured from differential waveform

3 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.

TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

INDUSTRY

LIMIT

UNITS

Notes

tjphPCIeG1

PCIe Gen 1

0.4

5

N/A

ps (p-p) 1,2,3,5

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

0.4

0.6

N/A

ps

(rms)

1,2,3,4,

5

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

0.1

0.2

N/A

ps

(rms)

1,2,3,4

tjphPCIeG3

PCIe Gen 3

(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)

0.050

0.1

N/A

ps

(rms)

1,2,3,4

tjph125M0

125MHz, 1.5MHz to 10MHz, -20dB/decade

rollover < 1.5MHz, -40db/decade rolloff > 10MHz

365

380

N/A

fs

(rms)

1,6

tjph125M1

125MHz, 12KHz to 20MHz, -20dB/decade

rollover < 1.5MHz, -40db/decade rolloff > 10MHz

535

550

N/A

fs

(rms)

1,6

1Guaranteed by design and characterization, not 100% tested in production.

4 For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2]

5 Driven by 9FGU0831 or equivalent

6 Rohde&Schartz SMA100

3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.

Additive Phase Jitter,

Bypass Mode

tjphPCIeG2

2 See http://www.pcisig.com for complete specs