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©2014-2025 Renesas Electronics Corporation

December 15, 2025

9DMU0141 Datasheet

Power Connections

Pin Descriptions

VDD

GND

21

34

12

11

Note: Pins 2 and 3 should be decoupled separately to

pins 1 and 4 respectively.

DIF outputs

Description

Pin Number

Input A receiver analog

Input B receiver analog

Pin#

Pin Name

Type

Pin Description

1

GNDR

GND

Analog Ground pin for the differential input (receiver)

2

VDDR1.5

PWR

1.5V power for differential input clock (receiver). This VDD should be treated as an Analog power rail

and filtered appropriately.

3

VDDR1.5

PWR

1.5V power for differential input clock (receiver). This VDD should be treated as an Analog power rail

and filtered appropriately.

4GNDR

GND

Analog Ground pin for the differential input (receiver)

5

DIF_INB

IN

HCSL Differential True input

6

DIF_INB#

IN

HCSL Differential Complement Input

7vSW_MODE

IN

Switch Mode. This pin selects either asynchronous or glitch-free, gapped clock switching of the mux.

Use asynchronous mode if 0 or 1 of the input clocks is running. Use Glitch-free mode If both input clocks

are running. This pin has an internal pull-down resistor of ~120kOhms and is dynamically configurable.

0 = asynchronous switching mode

1 = glitch-free, gapped clock switching mode

8^OE0#

IN

Active low input for enabling DIF pair 0. This pin has an internal pull-up resistor.

1 =disable outputs, 0 = enable outputs

9

DIF0

OUT

Differential true clock output

10

DIF0#

OUT

Differential Complementary clock output

11

GND

GND

Ground pin.

12

VDD1.5

PWR

Power supply, nominally 1.5V

13

NC

N/A

No Connection.

14

^SEL_A_B#

IN

Input to select differential input clock A or differential input clock B. This input has an internal pull-up

resistor.

0 = Input B selected, 1 = Input A selected.

15

DIF_INA

IN

HCSL Differential True input

16

DIF_INA#

IN

HCSL Differential Complement Input