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STM32F101C4 датащи(PDF) 63 Page - STMicroelectronics

номер детали STM32F101C4
подробное описание детали  Low-density access line, ARM®-based 32 bit MCU with 16 or 32 KB Flash, 5 timers, ADC and 4 communication interfaces
PDF  87 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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STM32F101C4 датащи(HTML) 63 Page - STMicroelectronics

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STM32F101x4, STM32F101x6
Electrical characteristics
86
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 40 are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 8.
Refer to Section 5.3.12: I/O current injection characteristics for more details on the
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 40. SPI characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master mode
0
18
MHz
Slave mode
0
18
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
Capacitive load: C = 30 pF
8
ns
tsu(NSS)(1)
1. Based on characterization, not tested in production.
NSS setup time
Slave mode
4 tPCLK
-
th(NSS)(1)
NSS hold time
Slave mode
73
-
tw(SCKH)(1)
tw(SCKL)(1)
SCK high and low time
Master mode, fPCLK = 36 MHz,
presc = 4
50
60
tsu(MI) (1)
Data input setup time
Master mode
SPI
1
-
tsu(SI)(1)
Data input setup time
Slave mode
-1
-
th(MI) (1)
Data input hold time
Master mode
SPI
1
-
th(SI)(1)
Data input
hold time
Slave mode
-
3
-
ta(SO)(1)(2)
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
Data output access time
Slave mode, fPCLK = 36 MHz,
presc = 4
055
Slave mode, fPCLK = 24 MHz
0
4 tPCLK
tdis(SO)(1)(3)
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
Data output disable time Slave mode
10
tv(SO) (1)
Data output valid time
Slave mode (after enable edge)
-
25
tv(MO)(1)
Data output valid time
Master mode (after enable
edge)
-
3
th(SO)(1)
Data output hold time
Slave mode (after enable edge)
25
-
th(MO)(1)
Master mode (after enable
edge)
4-



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