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STM32F101C4 датащи(PDF) 53 Page - STMicroelectronics

номер детали STM32F101C4
подробное описание детали  Low-density access line, ARM®-based 32 bit MCU with 16 or 32 KB Flash, 5 timers, ADC and 4 communication interfaces
PDF  87 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
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STM32F101C4 датащи(HTML) 53 Page - STMicroelectronics

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STM32F101x4, STM32F101x6
Electrical characteristics
86
5.3.13
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 33 are derived from tests
performed under the conditions summarized in Table 8. All I/Os are CMOS and TTL
compliant.
Table 33. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
Standard IO input low
level voltage
-
-0.3
-
0.28*(VDD-2 V)+0.8 V(1)
V
IO FT(2) input low
level voltage
-0.3
-
0.32*(VDD-2 V)+0.75 V(1)
VIH
Standard IO input high
level voltage
-
0.41*(VDD-2 V)+1.3 V(1)
-VDD+0.3
IO FT(2) input high
level voltage
VDD > 2 V
0.42*(VDD-2 V)+1 V(1)
-
5.5
VDD ≤ 2 V
5.2
Vhys
Standard IO Schmitt
trigger voltage
hysteresis(3)
-200
-
-
mV
IO FT Schmitt trigger
voltage hysteresis(3)
-5% VDD(4)
--
Ilkg
Input leakage current
(5)
VSS ≤ VIN ≤ VDD
Standard I/Os
--
±1
µA
VIN = 5 V
I/O FT
--
3
RPU
Weak pull-up
equivalent resistor(6)
VIN = VSS
30
40
50
k
Ω
RPD
Weak pull-down
equivalent resistor(6)
VIN = VDD
30
40
50
CIO
I/O pin capacitance
-
-
5
-
pF
1. Data based on design simulation.
2. FT = Five-volt tolerant. In order to sustain a voltage higher than VDD+0.3 the internal pull-up/pull-down resistors must be
disabled.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
4. With a minimum of 100 mV.
5. Leakage could be higher than max. if negative current is injected on adjacent pins.
6. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimum (~10% order)
.



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