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TDA7500A

Asynchronous Sample Rate Converter

The ASRC, embedded in the TDA7500A, offers a fully digital stereo asynchronous sample rate conversion of

digital audio sources to the TDA7500A's internal sample frequency. This solves the problem of mixing audio

sources with different sample rates and doesn't need the "classical" approach of synchronizing the PLL.

As the usual internal sample rate of TDA7500A is around 48.51 kHz, the ASRC works with the common input

signals only in upsampling mode. There is no need to explicitly program the input and output sample rates, as

the ASRC solves this problem with an automatic Digital Ratio Locked Loop.

The ASRC is intended for applications up to 20 bit input word width. Digital Audio Sources can be applied in

general Serial Audio Interface format (3 wires) as well as in AES/EBU, IEC and EIAJ CP-340 format (1 wire).

An interface to the DSP core offers the possibility of interrupt controlled sample delivery. Furthermore, a programma-

ble Control/Status Register inside the ASRC allows a great variety of adjustments and status informations.

Figure 18. shows, how the ASRC interfaces the other blocks.

PLL Clock Oscillator

The PLL Clock Oscillator can accept an external clock at XTI or it can be configured to run an internal oscillator

when a crystal is connected across pins XTI & XTO. There is an input divide block IDF (1 -> 32) at the XTI clock

input and a multiply block MF (9 -> 128) in the PLL loop. Hence the PLL can multiply the external input clock by

a ratio MF/IDF to generate the internal clock. This allows the internal clock to be within 1 MHz of any desired

frequency even when XTI is much greater than 1 MHz. It is recommended that the input clock is not divided

down to less than 1 MHz as this reduces the Phase Detector's update rate.

The clocks to the DSP can be selected to be either the VCO output divided by 2 to 16, or be driven by the

XTI pin directly.

The crystal oscillator and the PLL will be gated off when entering the power-down mode (by setting a reg-

ister on DSP0).

Figure 18. System Overview

Digital Audio Sources e.g.:

DAT

DAB

CD

MD

Broadcast

48 kHz 48 kHz 44.1 kHz 44.1 kHz

32 kHz

3

lrckr_slv

sckr_slv

sdi0

SAI Receiver

Channel 0

1

S/PDIF

Receiver

AES/EBU

IEC 958

EIAJ CP-340

Left [19:0]

Right [19:0]

Fsin

Left [19:0]

Right [19:0]

Fsin

ASRC

Master Clock

Source

Fsout * 256

DSP

Asynchr. Sample Rate Converter