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TDA7500A

FUNCTIONAL DESCRIPTION

The TDA7500A IC broken up into two distinct blocks. One block contains the two DSP Cores and their associ-

ated peripherals. The other contains the ADC, DAC and the RDS filter, demodulator and decoder.

24-BIT DSP CORE

The two DSP cores are used to process the audio and FM/AM data, coming from the ADC, either any kind of

digital data coming via SPDIF or SAI. After the digital signal processing these data are sent to the DAC for an-

alog conversion. Functions such as volume, tone, balance, and fader control, as well as spatial enhancement

and general purpose signal processing may be performed by the DSP0. When FM/AM mode is selected, DSP1

is fully devoted to AM/FM processing. Nevertheless it can be used for any kind of different application, when a

different input source is selected.

Some capabilities of the DSPs are listed below:

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Single cycle multiply and accumulate with convergent rounding and condition code generation

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2 x 56-bit Accumulators

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Double precision multiply

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Scaling and saturation arithmetic

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48-bit or 2 x 24-bit parallel moves

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64 interrupt vector locations

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Fast or long interrupts possible

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Programmable interrupt priorities and masking

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8 each of Address Registers, Address Offset Registers and Address Modulo Registers

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Linear, Reverse Carry, Multiple Buffer Modulo, Multiple Wrap-around Modulo address arithmetic

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Post-increment or decrement by 1 or by offset, Index by offset, predecrement address

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Repeat instruction and zero overhead DO loops

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Hardware stack capable of nesting combinations of 7 DO loops or 15 interrupts/subroutines

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Bit manipulation instructions possible on all registers and memory locations, also Jump on bit test

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4 pin serial debug interface

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Debug ccess to all internal registers, buses and memory locations

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5 word deep program address history FIFO

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Hardware and software breakpoints for both program and data memory accesses

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Debug Single stepping, Instruction injection and Disassembly of program memory

DSP PERIPHERALS

There are a number of peripherals that are tightly coupled to the two DSP Cores. Same of the peripherals are

connected to DSP 0 others are connected to DSP1.

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5.5k x 24-Bit Program RAM for DSP0

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1k x 24-Bit X-Data RAM for DSP0

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1k x 24-Bit Y-Data RAM for DSP0

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2k x 24-Bit Program RAM for DSP1

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1k x 24-Bit X-Data RAM for DSP1

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1k x 24-Bit Y-Data RAM for DSP1

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Serial Audio Interface (SAI)

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SPDIF receiver with sampling rate conversion