MPC8245 datasheet(58/68 Pages) FREESCALE

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MPC8245 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

Document Revision History

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Globally changed EPIC to PIC.

Section 1.4.1.4—Note 5: Changed register reference from 0x72 to 0x73.

Section 1.4.1.5—Table 5: Updated power dissipation numbers based on latest characterization data.

Section 1.4.2—Table 6: Updated table to show more thermal specifications.

Section 1.4.3—Table 7: Updated minimum memory bus value to 50 MHz.

Section 1.4.3.1—Changed equations for DLL locking range based on characterization data. Added

updates and reference to AN2164 for note 6. Added table defining Tdp parameters. Labeled N value

in Figures 5 through 8.

Section 1.4.3.2—Table 10: Changed bit definitions for tap points. Updated note on Tos and added

reference to AN2164 for note 7. Updated Figure 9 to show significance of Tos.

Section 1.4.3.4—Added column for SDRAM_CLK @ 133 MHz

Sections 1.5.1 and 1.5.2—Corrected packaging information to state TBGA packaging.

Section 1.5.3—Corrected some signals in Table 16 which were missing overbars in the Rev 1.0

release of the document.

Section 1.6—Updated Note 10 of Tables 18 and 19.

Section 1.7.3—Changed sentence recommendation regarding decoupling capacitors.

Section 1.9—Updated format of tables in Ordering Information section.

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Updated document template.

Section 1.4.1.4—Changed the driver type names in Table 6 to match with the names used in the

MPC8245 Reference Manual.

Section 1.5.3—Updated driver type names for signals in Table 16 to match with names used in the

MPC8245 Integrated Processor Reference Manual.

Section 1.4.1.2—Updated Table 7 to refer to new PLL Tables for VCO limits.

Section 1.4.3.3—Added item 12e to Table 10 for SDRAM_SYNC_IN to Output Valid timing.

Section 1.5.1—Updated solder balls information to 62Sn/36PB/2Ag.

Section 1.6—Updated PLL Tables 17 and 18 and appropriate notes to reflect changes of VCO ranges

for memory and CPU frequencies.

Section 1.7—Updated voltage sequencing requirements in Table 2 and removed Section 1.7.2.

Section 1.7.8—Updated TRST information and Figure 26.

New Section 1.7.2—Updated the range of I/O power consumption numbers for OVDD and GVDD to

correct values as in Table 5. Updated fastest frequency combination to 66:100:350 MHz.

Section 1.7.9—Updated list for heat sink and thermal interface vendors.

Section 1.9—Changed format of Ordering Information section. Added tables to reflect part number

specifications also available.

Added Sections 1.9.2 and 1.9.3.

0.5

—

Corrected labels for Figures 5 through 8.

Table 19. Revision History Table (continued)

Revision

Date

Substantive Change(s)

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