MPC8245 datasheet(56/68 Pages) FREESCALE

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MPC8245 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

Document Revision History

Table 19 provides a revision history for this hardware specification.

Table 19. Revision History Table

Revision

Date

Substantive Change(s)

8/07

Section 3, Table 3, and Table 7—Changed format of recommended voltage supply values so that delta

to the chosen nominal does not exceed ± 100 mV.

Completely replaced Section 4.6 with compliant I2C specifications as with other related integrated

processor devices.

12/27/05

Document—Added Power Architecture information.

Section 4.1—Changed increased absolute maximum range for VDD in Table 1. Updated format of

nominal voltage listings in Table 2.

Section 9.2—Removed Note 3 from Table 21.

Updated back page information.

11/15/2005 Document—Imported new template and made minor editorial changes.

Removed references to a 466 MHz part since it is not available for new orders.

Section 4.3.2—Added paragraph for using DLL mode that provides lowest locked tap point read in

0xE3.

Section 5.3—Updated the driver and I/O assignment information for the multiplexed PCI clock and

DUART signals. Added note for HRST_CPU and HRST_CTRL, which had been mentioned only in

Figure 2.

Section 9.2—Updated the part ordering specifications for the extended temperature parts. Also

updated the section to reflect what we offer for new orders.

Section 9.3—Added new section, “Part Marking.” Updated Figure 33 to match with current part

marking format.

10/07/2004 Section 4.1.2—Table 2: Corrected range of AVDD and AVDD2.

Section 9.1—Table 21: Corrected voltage range under Process Descriptor column. Minor reformatting.

6.1

05/24/2004 Section 4.5.3—Table 11: Spec 12b was improved from 4.5 ns to 4.0 ns. This improvement is

guaranteed on devices marked after work week (WW) 28 of 2004. A device's work week may be

determined from the “YYWW” portion of the devices trace ability code which is marked on the top of

the device. So for WW28 in 2004, the device’s YYWW is marked as 0428. For more information refer

to Figure 33

05/11/2004 Section 4.1.2—Table 2: Corrected range of GVDD to 3.3 ± 5%.

Section 4.2.1—Table 4: Changed the default for drive strength of DRV_STD_MEM.

Section 4.5.1—Table 8: Changed the wording description for item 15.

Section 4.5.2—Table 10: Changed Tos range and wording in note; Figure 11:changed wording for

SDRAM_SYNC_IN description relative to TOS.

Section 4.5.3—Table 11: Changed timing specification for sys_logic_clk to output valid (memory

control, address, and data signals).

5.1

—

Section 4.3.1—Table 9: Corrected last row to state the correct description for the bit setting. Max tap

delay, DLL extend. Figure 8: Corrected the label name for the DLL graph to state “DLL Locking Range

Loop Delay vs. Frequency of Operation for DLL_Extend=1 and Normal Tap Delay”

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