TAS5706PAP datasheet(22/62 Pages) TI

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DETAILED DESCRIPTION

POWER SUPPLY

CLOCK, AUTO DETECTION, AND PLL

SERIAL DATA INTERFACE

PWM Section

2C COMPATIBLE SERIAL CONTROL INTERFACE

TAS5706

SLOS550A – DECEMBER 2007 – REVISED DECEMBER 2007

The digital portion of the chip requires 3.3 V, and the power stages can work from 10 V to 26 V.

The TAS5706 DAP is a slave device. It accepts MCLK, SCLK, and LRCLK. The digital audio processor (DAP)

supports all the sample rates and MCLK rates that are defined in the clock control register.

The TAS5706 checks to verify that SCLK is a specific value of 32 fS, 48 fS, or 64 fS. The DAP only supports a 1 ×

fS LRCLK. The timing relationship of these clocks to SDIN1/2 is shown in subsequent sections. The clock section

uses MCLK or the internal oscillator clock (when MCLK is unstable or absent) to produce the internal clock.

The DAP can autodetect and set the internal clock control logic to the appropriate settings for the frequencies of

32 kHz, normal speed (44.1 or 48 kHz), double speed (88.2 kHz or 96 kHz), and quad speed (176.4 kHz or

192 kHz). The automatic sample rate detection can be disabled and the values set via I2C in the clock control

The DAP also supports an AM interference-avoidance mode during which the clock rate is adjusted, in concert

with the PWM sample rate converter, to produce a PWM output at 7

× f

S, 8 × fS, or 6 × fS.

The sample rate must be set manually during AM interference avoidance and when de-emphasis is enabled.

Serial data is input on SDIN1/2. The PWM outputs are derived from SDIN1/2. The TAS5706 DAP accepts 32-,

44.1-, 48-, 88.2-, 96-, 176.4-, and 192-kHz serial data in 16-, 18-, 20-, or 24-bit data in left-justified, right-justified,

and I2S serial data formats.

The TAS5706 DAP device uses noise-shaping and sophisticated error correction algorithms to achieve high

power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper that

has >100-dB SNR performance from 20 Hz to 20 kHz. The PWM section accepts 24-bit PCM data from the DAP

and outputs four PWM audio output channels. TAS5706 PWM section output supports bridge-tied loads.

The PWM section has individual channel dc blocking filters that can be enabled and disabled. The filter cutoff

frequency is less than 1 Hz. Individual channel de-emphasis filters for 32-, 44.1-, and 48-kHz are included and

can be enabled and disabled.

Finally, the PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%.

The TAS5706 DAP has an I2C serial control slave interface to receive commands from a system controller. The

serial control interface supports both normal-speed (100-kHz) and high-speed (400-kHz) operations without wait

states. As an added feature, this interface operates even if MCLK is absent.

The serial control interface supports both single-byte and multi-byte read and write operations for status registers

and the general control registers associated with the PWM.

The I2C interface supports a special mode which permits I2C write operations to be broken up into multiple-data

write operations that are multiples of 4 data bytes. These are 6-, 10-, 14-, 18-, ... etc., -byte write operations that

are composed of a device address, read/write bit, subaddress, and any multiple of 4 bytes of data. This permits

the system to write large register values incrementally without blocking other I2C transactions.

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