TAS5706PAP datasheet(9/62 Pages) TI

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DISSIPATION RATINGS

RECOMMENDED OPERATING CONDITIONS

PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS

PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS

TAS5706

SLOS550A – DECEMBER 2007 – REVISED DECEMBER 2007

TA = 25°C

TA = 45°C

TA = 70°C

PACKAGE(1)

DERATING FACTOR

POWER RATING

10-mm

× 10-mm QFP

29 mW/

°C

2.89 W

2.31 W

1.59 W

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

Digital/analog supply voltage

DVDD

3.3

3.6

Half-bridge supply voltage

PVCC_xx

VIH

High-level input voltage

3.3-V TTL, 5-V tolerant

VIL

Low-level input voltage

3.3-V TTL, 5-V tolerant

0.8

Operating ambient temperature range

°C

Operating junction temperature range

150

°C

RL (BTL)

6.0

RL (SE)

Load impedance

Output filter: L = 22

µH, C = 680 nF.

3.2

Ω

RL (PBTL)

3.2

LO (BTL)

Minimum output inductance under

LO (SE)

Output-filter inductance

µH

short-circuit condition

LO (PBTL)

PARAMETER

TEST CONDITIONS

MODE

VALUE

UNITS

32–kHz data rate ±2%

× sample rate

384

kHz

Output sample rate 2

×–1×

44.1-, 88.2-, 176.4-kHz data rate ±2%

×, 4×, and 2× sample rates

352.8

kHz

oversampled

48-, 96-, 192-kHz data rate ±2%

×, 4×, and 2× sample rates

384

kHz

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fMCLKI

Frequency, MCLK (1 / tcyc2)

4.9

MHz

MCLK duty cycle

40%

50%

60%

≥2-V MCLK = 49.152 MHz, within the

MCLK minimum high time

min and max duty cycle constraints

≤0.8-V MCLK = 49.152 MHz, within the

MCLK minimum low time

min and max duty cycle constraints

LRCLK allowable drift before LRCLK reset

MCLKs

External PLL filter capacitor C1

SMD 0603 Y5V

External PLL filter capacitor C2

SMD 0603 Y5V

4.7

External PLL filter resistor R

SMD 0603, metal film

470

Ω

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