IP113F
Preliminary Data Sheet
Extended MII registers and EEPROM registers (continued)
MII
ROM
NAME
R/W
DESCRIPTION
DEFAULT
Switch configuration register 3 (MII register 31D)
31.0
--
software_reset
R/W
SC
Chip software reset
It is a self-clear bit. All registers are not
affected after the software reset is asserted.
1: reset, 0: not reset
0
31.1
--
mg_power_indicate
_disable
R/W
IP113F power abnormal indication disable
1: disable power abnormal notice
0: enable power abnormal notice
0
31[3:2]
--
link_list_fail
RO
Link list failure indication
bit[2] : TP port link list abnormal
bit[3] : Fiber port link list abnormal
1: fail
0: ok
00
31[5:4]
--
BIST_status
RO
BIST Status of embedded SSRAM
bit[4] : memory is under testing
1: under testing, 0: testing over
bit[5] : memory test result is good when
testing over
1: good, 0: fail
01
31[6]
--
mg_auto_loopback
_test
R/W
Auto loopback test enable
1: enable, 0:disable
0
31[7]
--
mg_t2_timer
_disable
R/W
Loopback test T2 timer disable (TS-1000)
1: The MC will not send loopback end
indication MF when T2 timer expired
0: The MC will send loopback end MF when
T2 timer expired
0
31[8]
--
mg_auto_loopback
_complete
RO
Auto loopback test complete
1: completed, 0: still testing
0
31[9]
--
mg_auto_loopback
_ok
RO
Auto loopback test OK
1: good, 0: fail
0
31[15:10]
--
Reserved
Confidential.
44/46
Aug. 20, 2003
Copyright © 2003, IC Plus Corp.
IP113F-DS-R02
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