C8051F360 datasheet(67/289 Pages) SILABS

67 / 289 page

C8051F360/1/2/3/4/5/6/7/8/9

Rev. 1.1

Voltage Reference (C8051F360/1/2/6/7/8/9)

The Voltage reference MUX on the C8051F360/1/2/6/7/8/9 devices is configurable to use an externally

connected voltage reference, the internal reference voltage generator, or the VDD power supply voltage

(see Figure 7.1). The REFSL bit in the Reference Control register (REF0CN) selects the reference source.

For an external source or the internal reference, REFSL should be set to ‘0’. To use VDD as the reference

source, REFSL should be set to ‘1’.

The BIASE bit enables the internal voltage bias generator, which is used by the ADC, Temperature Sensor,

internal oscillators, and Current DAC. This bias is enabled when any of the aforementioned peripherals are

enabled. The bias generator may be enabled manually by writing a ‘1’ to the BIASE bit in register

REF0CN; see SFR Definition 7.1 for REF0CN register details. The electrical specifications for the voltage

reference circuit are given in Table 7.1.

The internal voltage reference circuit consists of a 1.2 V, temperature stable bandgap voltage reference

generator and a gain-of-two output buffer amplifier. The internal voltage reference can be driven out on the

VREF pin by setting the REFBE bit in register REF0CN to a ‘1’ (see SFR Definition 7.1). The maximum

load seen by the VREF pin must be less than 200 µA to GND. When using the internal voltage reference,

bypass capacitors of 0.1 µF and 4.7 µF are recommended from the VREF pin to GND. If the internal refer-

ence is not used, the REFBE bit should be cleared to ‘0’. Electrical specifications for the internal voltage

reference are given in Table 7.1.

Important Note about the VREF Pin: Port pin P0.3 on the C8051F360 device and P0.0 on

C8051F361/2/6/7/89 devices is used as the external VREF input and as an output for the internal VREF.

When using either an external voltage reference or the internal reference circuitry, the port pin should be

configured as an analog pin, and skipped by the Digital Crossbar. To configure the port pin as an analog

pin, set the appropriate bit to ‘0’ in register P0MDIN. To configure the Crossbar to skip the VREF port pin,

set the appropriate bit to ‘1’ in register P0SKIP. Refer to Section “17. Port Input/Output” on page 182 for

Figure 7.1. Voltage Reference Functional Block Diagram

VREF

(to ADC)

To Analog Mux

VDD

VREF

VDD

External

Voltage

Reference

Circuit

GND

Temp Sensor

Bias Generator

To ADC, IDAC,

Internal Oscillators

IOSCE

REF0CN

REFBE

Internal

Reference

Recommended Bypass

Capacitors

4.7

μF0.1μF

C8051F360 датащи(PDF) 67 Page - Silicon Laboratories

C8051F360 датащи(HTML) 67 Page - Silicon Laboratories

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL