C8051F360 datasheet(57/289 Pages) SILABS

57 / 289 page

C8051F360/1/2/3/4/5/6/7/8/9

Rev. 1.1

SFR Definition 5.6. ADC0CN: ADC0 Control

Bit 7:

AD0EN: ADC0 Enable Bit.

0: ADC0 Disabled. ADC0 is in low-power shutdown.

1: ADC0 Enabled. ADC0 is active and ready for data conversions.

Bit 6:

AD0TM: ADC0 Track Mode Bit.

0: Normal Track Mode: When ADC0 is enabled, tracking is continuous unless a conversion is

in progress.

1: Low-power Track Mode: Tracking Defined by AD0CM2-0 bits (see below).

Bit 5:

AD0INT: ADC0 Conversion Complete Interrupt Flag.

0: ADC0 has not completed a data conversion since the last time AD0INT was cleared.

1: ADC0 has completed a data conversion.

Bit 4:

AD0BUSY: ADC0 Busy Bit.

Read:

0: ADC0 conversion is complete or a conversion is not currently in progress. AD0INT is set to

logic ‘1’ on the falling edge of AD0BUSY.

1: ADC0 conversion is in progress.

Write:

0: No Effect.

1: Initiates ADC0 Conversion if AD0CM2-0 = 000b

Bit 3:

AD0WINT: ADC0 Window Compare Interrupt Flag.

0: ADC0 Window Comparison Data match has not occurred since this flag was last cleared.

1: ADC0 Window Comparison Data match has occurred.

Bits 2

–0: AD0CM2–0: ADC0 Start of Conversion Mode Select.

When AD0TM = 0:

000: ADC0 conversion initiated on every write of ‘1’ to AD0BUSY.

001: ADC0 conversion initiated on overflow of Timer 0.

010: ADC0 conversion initiated on overflow of Timer 2.

011: ADC0 conversion initiated on overflow of Timer 1.

100: ADC0 conversion initiated on rising edge of external CNVSTR.

101: ADC0 conversion initiated on overflow of Timer 3.

11x: Reserved.

When AD0TM = 1:

000: Tracking initiated on write of ‘1’ to AD0BUSY and lasts 3 SAR clocks, followed by con-

version.

001: Tracking initiated on overflow of Timer 0 and lasts 3 SAR clocks, followed by conversion.

010: Tracking initiated on overflow of Timer 2 and lasts 3 SAR clocks, followed by conversion.

011: Tracking initiated on overflow of Timer 1 and lasts 3 SAR clocks, followed by conversion.

100: ADC0 tracks only when CNVSTR input is logic low; conversion starts on rising CNVSTR

edge.

101: Tracking initiated on overflow of Timer 3 and lasts 3 SAR clocks, followed by conversion.

11x: Reserved

SFR Page:

SFR Address:

all pages

0xE8

(bit addressable)

R/W

Reset Value

AD0EN

AD0TM

AD0INT AD0BUSY AD0WINT AD0CM2

AD0CM1

AD0CM0 00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

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