CY28342

Rev 1.0, November 20, 2006

Page 9 of 21

Byte 12: Watchdog Time Stamp Register (All bits are Read and Write functional)

Bit

@Pup

Name

Description

71

SRESET#/PCI_STP#. 1 = pin 12 is the input pin as PCI_STP# signal. 0 = pin 12 is the output pin

as SRESET# signal.

60

Frequency Revert. This bit allows setting the Revert Frequency once the system is rebooted due

to Watchdog time-out only. 0 = selects frequency of existing H/W setting. 1 = selects frequency of

the second to last S/W setting (the software setting prior to the one that caused a system reboot).

50

WDTEST. For WD-Test, ALWAYS program to “0.”

40

WD Alarm. This bit is set to “1” when the Watchdog times out. It is reset to “0” when the system

clears the WD time stamps (WD3:0).

3

0

WD3

These bits select the Watchdog Time Stamp Value. See Table 8.

20

WD2

10

WD1

00

WD0

Table 8. Watchdog Time Stamp Table

WD(3:0)

FUNCTION

0000

Off

0001

1 second

0010

2 seconds

0011

3 seconds

0100

4 seconds

0101

5 seconds

0110

6 seconds

0111

7 seconds

1000

8 seconds

1001

9 seconds

1010

10 seconds

1011

11 seconds

1100

12 seconds

1101

13 seconds

1110

14 seconds

1111

15 seconds

Bit

@Pup

Description

7

0

Reserved.

60

N6, MSB

50

N5

40

N4

30

N3

20

N2

10

N3

00

N0, LSB

Note:

5. Byte 13 and Byte 14 should be Write together in every case.