CY28342

Rev 1.0, November 20, 2006

Page 6 of 21

Since SDR and DDR Zero Delay Buffers will share this same address, the device starts from Byte 4.

30:37

Data byte from slave – 8 bits

38

Not acknowledge

39

Stop

Byte 4: CPU Clock Register (All bits are Read and Write functional)

Bit

@Pup

Pin#

Name

Description

7

H/W Setting

14

FS3

For selecting frequencies in Table 1.

6

H/W Setting

4

FS2

For selecting frequencies in Table 1.

5

H/W Setting

3

FS1

For selecting frequencies in Table 1.

4

H/W Setting

2

FS0

For selecting frequencies in Table 1.

3

0

0 = HW, 1 = SW frequency selection.

2

H/W Setting

15

FS4

For selecting frequencies in Table 1.

1

1

SSCG

Spread Spectrum Enable. 0 = spread off, 1 = spread on.

This is a Read and Write control bit.

0

0

Master output control 0 = running, 1 = three-state all outputs.

Table 4. Byte Read and Byte Write Protocol (continued)

Byte Write Protocol

Byte Read Protocol

Bit

Description

Bit

Description

Byte 5: CPU Clock Register (all bits are Read-only)

Bit

@Pup

Pin#

Name

Description

70

Reserved.

60

Reserved.

5

X

26

MULT0

MULT0 (pin 26) value. This bit is Read-only.

4

X

15

FS4

FS4 Read-back. This bit is Read-only.

3

X

14

FS3

FS3 Read-back. This bit is Read-only.

2

X

4

FS2

FS2 Read-back. This bit is Read-only.

1

X

3

FS1

FS1 Read-back. This bit is Read-only.

0

X

2

FS0

FS0 Read-back. This bit is Read-only.

Byte 6: CPU Clock Register (All bits are Read and Write functional)

Bit

@Pup

Pin#

Name

Description

7

0

Function Test Bit. Always program to 0.

6

0

Reserved.

5

0

14

PCI_F0

PCI_STP# control of PCI_F0. 0 = free running, 1 = stopped when PCI_STP# is LOW.

4

0

15

PCI_F1

PCI_STP# control of PCI_F1. 0 = free running, 1 = stopped when PCI_STP# is LOW.

3

1

40,39

CPU0T/C

Controls CPU0T and CPU0C functionality when CPU_STP# is asserted LOW.

0 = free running, 1 = stopped with CPU_STP# asserted LOW.

This is a Read and Write control bit.

20

44,43

CPU1T/C

Controls CPU1T and CPU1C functionality when CPU_STP# is asserted LOW

0= Free Running, 1 Stopped with CPU_STP# asserted to LOW.

This and Read and Write control bit.

1

1

40,39

CPU0T/C

CPU0T, CPU0C output control, 1= enabled, 0 = disabled.

This is a Read and Write control bit.

01

44,43

CPU1T/C

CPU1T, CPU1C output control, 1= enabled, 0 = disabled.

This is a Read and Write control bit.