CY28342

Rev 1.0, November 20, 2006

Page 8 of 21

Byte 11: Dial-a-Skew™ and Dial-a-Ratio™ Control Register (All bits are Read and Write functional)

Bit

@Pup

Name

Description

7

0

DARSD2 Programming these bits allows modifying the frequency ratio of the SDCLK clock relative to the VCO.

See Table 5.

6

0

DARSD1

5

0

DARSD0

4

0

DARAG2 Programming these bits allows modifying the frequency ratio of the AGP(1:0), PCI(5:0) and PCIF(0:1)

clocks relative to the VCO. See Table 6.

3

0

DARAG1

2

0

DARAG0

1

0

DASSD1 Programming these bits allows shifting skew between CPU and SDCLK signals. See Table 7.

0

0

DASSD0

Table 5. Dial-a-Ratio SDCLK

DARSD (2:0)

VC0/SDCLK ratio

000

Frequency selection default

001

2

010

3

011

4

100

5

101

6

110

8

111

9

DARAG (2:0)

VC0/AGP Ratio

000

Frequency selection default

001

6

010

7

011

8

100

9

101

10

110

10

111

10

Table 7. Dial-a-Skew SDCLK CPU

DASSD (1:0)

SDCLK-CPU Skew

00

01

+150 ps (CPU lag)*

10

+300 ps (CPU lag)*

11

+450 ps (CPU lag)*

Notes:

3. The ratio of AGP to PCI is retained at 2:1.

4. See Figure 8 for CPU measurement point. See Figure 9 for SDCLK measurement point.