CY28316

Rev 1.0, November 20, 2006

Page 9 of 17

Byte 13: Programmable Frequency Select N-Value Register

Bit

Name

Default

Pin Description

Bit 7

CPU_FSEL_N7

0

If Prog_Freq_EN is set, CY28316 will use the values programmed in

CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output

frequency. The new frequency will start to load whenever CPU_FSELM[6:0]

is updated. The setting of the FS_Override bit determines the frequency ratio

for CPU, SDRAM, and PCI. When it is cleared, CY28316 will use the same

frequency ratio stated in the Latched FS[4:0] register. When it is set, CY28316

will use the frequency ratio stated in the SEL[4:0] register. CY28316 supports

programmable CPU frequencies ranging from 50 MHz to 248 MHz.

Bit 6

CPU_FSEL_N6

0

Bit 5

CPU_FSEL_N5

0

Bit 4

CPU_FSEL_N4

0

Bit 3

CPU_FSEL_N3

0

Bit 2

CPU_FSEL_N2

0

Bit 1

CPU_FSEL_N1

0

Bit 0

CPU_FSEL_N0

0

Byte 14: Programmable Frequency Select M-Value Register

Bit

Name

Default

Description

Bit 7

Pro_Freq_EN

0

Programmable output frequencies enabled.

0 = Disabled.

1 = Enabled.

Bit 6

CPU_FSEL_M6

0

If Prog_Freq_EN is set, CY28316 will use the values programmed in

CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output

frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is

updated. The setting of the FS_Override bit determines the frequency ratio for

CPU, SDRAM, and PCI. When it is cleared, CY28316 will use the same

frequency ratio stated in the Latched FS[4:0] register. When it is set, CY28316

will use the frequency ratio stated in the SEL[4:0] register. CY28316 supports

programmable CPU frequencies ranging from 50 MHz to 248 MHz.

Bit 5

CPU_FSEL_M5

0

Bit 4

CPU_FSEL_M4

0

Bit 3

CPU_FSEL_M3

0

Bit 2

CPU_FSEL_M2

0

Bit 1

CPU_FSEL_M1

0

Bit 0

CPU_FSEL_M0

0

Byte 15: Reserved Register

Bit

Pin#

Name

Default

Description

Bit 7

–

Reserved

0

Reserved.

Bit 6

–

Reserved

0

Reserved.

Bit 5

–

Reserved

0

Reserved.

Bit 4

–

Reserved

0

Reserved.

Bit 3

–

Reserved

0

Reserved.

Bit 2

–

Vendor test mode

0

Reserved. Write with ‘0.’

Bit 1

–

Vendor test mode

1

Test mode. Write with ‘1.’

Bit 0

–

Vendor test mode

1

Test mode. Write with ‘1.’

Byte 16: Reserved Register

Bit

Pin#

Name

Default

Description

Bit 7

–

Reserved

0

Reserved.

Bit 6

–

Reserved

0

Reserved.

Bit 5

–

Reserved

0

Reserved.

Bit 4

–

Reserved

0

Reserved.

Bit 3

–

Reserved

0

Reserved.

Bit 2

–

Reserved

0

Reserved.

Bit 1

–

Reserved

0

Reserved.

Byte 17: Reserved Register

Bit

Pin#

Name

Default

Description

Bit 7

–

Reserved

0

Reserved.

Bit 6

–

Reserved

0

Reserved.