Rev 1.4, May 28, 2007

Page 4 of 18

SL23EP08

Figure 1. CLKIN Input to CLKA and CLKB Delay

S2

S1

Clock A1-A4

Clock B1-B4

Output Source

PLL Shutdown

and Bypass

0

0

Tri-state

Tri-state

PLL

Yes

0

1

Driven

Tri-state

PLL

No

1

0

Driven

Driven

Reference(CLKIN)

Yes

1

1

Driven

Driven

PLL

No

Table 2. Select Input Decoding

Device

Feedback From

Bank-A Frequency

Bank-B Frequency

SL23EP08-1 and 1H

Bank-A or Bank-B

Reference

Reference

SL23EP08-2 and -2H

[1]

Bank-A

Reference

Reference/2

SL23EP08-2 and -2H

[1]

Bank-B

2x Reference

Reference

SL23EP08-3

[1]

Bank-A

2xReference

Reference

[2]

SL23EP08-3

[1]

Bank-B

4xReference

2xReference

SL23EP08-4

Bank-A or Bank-B

2x Reference

2x Reference

SL23EP08-5H

Bank-A or Bank-B

Reference/2

Reference/2

Table 3. Available SL23EP08 Configurations

Notes:

1. Outputs are inverted on SL23EP08-2, -2H and -3 in PLL bypass mode when S2=1 and S1=0. Use SL23EP08-1 if

non-inverting outputs are required.

2. Output phase is random (0° or 180° with respect to input clock). Use SL23EP08-2 if phase integrity is required.