Rev 1.4, May 28, 2007

Page 14 of 18

SL23EP08

Switching Electrical Characteristics (I-Grade-Cont.)

Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85°C

Output Duty Cycle

DC3

CL=15pF, Fout=66 MHz, all versions

Measured at VDD/2

45

50

55

%

Output Duty Cycle

DC4

CL=15pF, Fout=133 MHz, all versions

Measured at VDD/2

45

50

55

%

Output Duty Cycle

DC5

CL=15pF, Fout=166 MHz, all versions

Measured at VDD/2

40

50

60

%

Output Rise/Fall Time

tr/f1

CL=30pF, -1, -2 and -4 versions

Measured at 0.6 to 1.8V

-

-

2.2

ns

Output Rise/Fall Time

tr/f2

CL=15pF, -1, -2 and -4 versions

Measured at 0.6 to 1.8V

-

-

1.8

ns

Output Rise/Fall Time

tr/f3

CL=30pF, -1H and -2H and versions

Measured at 0.6 to 1.8V

-

-

1.5

ns

Output Rise/Fall Time

tr/f4

CL=15pF, -1H and -2H and versions

Measured at 0.6 to 1.8V

-

-

1.2

ns

Output-to-Output Skew

on Same Bank

SKW2

-1 and -2, measured from 0.8V to

2.0V, and outputs are equally loaded

-

100

220

ps

Output-to-Output Skew

on Same Bank

SKW2

-1H and -2H and -4, measured at

VDD/2 and outputs are equally loaded

-

100

220

ps

Output-to-Output Skew

Between Bank A and B

SKW3

-1, -1H, 2H and -4, measured at

VDD/2 and outputs are equally loaded

-

100

220

ps

Output-to-Output Skew

Between Bank A and B

SKW4

-2, measured at VDD/2 and outputs

are equally loaded

-

180

375

ps

Device-to-Device Skew

SKW5

All versions, measured at VDD/2 and

outputs are equally loaded

-

275

550

ps

Input-to-Output Delay

Dt

All versions, CLKIN to FBK rising

edge, measured at VDD/2 and outputs

are equally loaded and S2=S1=1

-200

-

200

ps

Fout=66 MHz and CL=15pF

-

80

175

ps

Cycle-to-Cycle Jitter

(-1, -2 and -4 Versions)

CCJ1

Fout=133MHz and CL=15pF

-

70

150

ps

Fout=66 MHz and CL=15pF

-

70

150

ps

Cycle-to-Cycle Jitter

(-1H and -2H Versions)

CCJ2

Fout=166MHz and CL=15pF

-

60

125

ps

PLL Lock Time

tLOCK

From 0.95VDD and valid CLKIN

-

-

1.0

ms